Random Discrete Dopant Induced Variability in Negative Capacitance Transistors

In this work we investigate the impact of random discrete dopants (RDD) induced statistical variability in ferroelectric negative capacitance field effect transistors (NCFETs). We couple the 3D `atomistic' statistical device simulator GARAND with the Landau - Khalatnikov equation of the ferroelectric for this study. We found that the negative capacitance effect provided by the ferroelectric layer can lead to suppression of the RDD induced variability in the threshold voltage (Vt), OFF-current (IOFF), and ON-current (ION). This immunity to RDD induced variability increases with increase in the ferroelectric thickness

Interplay of RDF and Gate LER Induced Statistical Variability in Negative Capacitance FETs

The downscaling of traditional DRAM [1] is facing challenges due to the presence of external capacitor. Z2FET [2-5] has been demonstrated as a promising DRAM candidate eliminating the need for external capacitor. In the past, attention was focused on the optimization of device structure [5] and fabrication process [2] without paying much attention to the Statistical (local) Variability (SV) which is crucial for any memory technology. In this paper, a novel simulation methodology is proposed and the SV of DRAM Memory Window (MW) is investigated systematically. It is found that SV of MW is dominated by Metal Gate Granularity (MGG) coming from the Gated-SOI region of the Z2FET. Although Random Discrete Dopant (RDD) induced variations in the threshold voltage (Vth) has larger spread in the Intrinsic-SOI part, it has no significant effect on the overall Z2FET characteristics. Based on the proposed methodology, SV of MW at different process corners has also been studied. Results reveal the necessity for further process optimization due to the best corner giving rise not only to larger average MW but also less variations. Furthermore, circuit level read performance (including the variability) of a Z2FET-based memory cell have been evaluated. All these findings could guide the further performance optimization from both device and memory cell circuit point of view for Z2FET-based volatile memory product development

An Exploration of Potential Pathways Toward Emerging Electronic Devices with Ferroelectric Materials

In the relentless pursuit of Moore's law, device scaling down to the nanometer regime has gradually reached a bottleneck as the power dissipation in microchips becomes a more and more challenging concern. Therefore, emerging technologies beyond CMOS are in urgent need of development. Among many proposed emerging devices, we primarily focus our research attention on the negative capacitance phenomenon in ferroelectrics and the magnetoelectric effect in multiferroics for low power device applications in this thesis. To assess the potential application of the negative capacitance effect, we first implement a physics-based circuit-compatible model of single domain ferroelectric materials for the study of the performance of negative capacitance field-effect transistors at the device and circuit levels. The single domain ferroelectric model is further extended to a multi-domain model by adopting the phase field formalism to capture the polycrystalline nature of ferroelectric films. For realistic logic device applications, however, the physical mechanisms behind the experimental observation of hysteresis-free negative capacitance behaviors have not yet been clear. Therefore, we dedicate our research efforts to the study of such a key phenomenon for the realization of ultra-low power negative capacitance field effect transistors. In addition, with proper free energy contributions included to describe the experimentally observed two-step polarization switching process in bismuth ferrite, a unified micromagnetic/ferroelectric simulation framework is developed to model the deterministic switching dynamics and thermal stability of the single-domain BFO/CoFe heterojunction. Lastly, a comprehensive thesis overview and the important topics for future works are given, especially the trapped charge dynamics in ferroelectric field effect transistors, which is the major reliability concern for the memory device realization.Ph.D