Fully differential implementation of a delta-sigma modulator based on the pseudo-pseudo differential technique

Flicker noise and distortion are the main limitations in biomedical applications, especially for Switched Capacitor implementations, where the flicker noise is folded into the signal band. To remove the flicker noise and increase the linearity, the Pseudo-Pseudo Differential (P2D) technique has been proposed, where a single-ended signal is processed in a differential way. This paper presents the first silicon implementation of a second order Comparator-Based Switched-Capacitor (CBSC) delta-sigma modulator based on a variation of the P2D technique. Experimental results in a standard 180 nm CMOS technology show an improvement of 10 dB in the Peak SNDR, 5 dB in the DR, and 9 dB in the SFDR over its pseudo differential counterpart, which is the preferred differential implementation for CBSC circuits. Moreover, it is achieved with a reduction in the power consumption

Behavioral modeling of low-frequency noise in switched-capacitor circuits using Python

In precision circuits validating the performance in the presence of low-frequency noise is particularly challenging especially at transistor level, as long simulations are required to observe the low frequency performance. However, running such system-level simulations is rarely practical at transistor level as these simulations can take days to weeks to complete. This work presents a high-level model in Python for generating low-frequency noise which can be used for validating the low-frequency performance of a design in a timely manner. Simulation times can be reduced from days to minutes, enabling designers to achieve a high-level simulation coverage. With Python and NumPy this can be achieved using open-source software tools at no cost

12.8 kHz Energy-Efficient Read-Out IC for High Precision Bridge Sensor Sensing System

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 김수환.In the thesis, a high energy-efficient read-out integrated circuit (read-out IC) for a high-precision bridge sensor sensing system is proposed. A low-noise capacitively-coupled chopper instrumentation amplifier (CCIA) followed by a high-resolution incremental discrete-time delta-sigma modulator (DTΔΣΜ) analog-to-digital converter (ADC) is implemented. To increase energy-efficiency, CCIA is chosen, which has the highest energy-efficiency among IA types. CCIA has a programmable gain of 1 to 128 that can amplify the small output of the bridge sensor. Impedance boosting loop (IBL) is applied to compensate for the low input impedance, which is a disadvantage of a CCIA. Also, the sensor offset cancellation technique was applied to CCIA to eliminate the offset resulting from the resistance mismatch of the bridge sensor, and the bridge sensor offset from -350 mV to 350 mV can be eliminated. In addition, the output data rate of the read-out IC is designed to be 12.8 kHz to quickly capture data and to reduce the power consumption of the sensor by turning off the sensor and read-out IC for the rest of the time. Generally, bridge sensor system is much slower than 12.8 kHz. To suppress 1/f noise, system level chopping and correlated double sampling (CDS) techniques are used. Implemented in a standard 0.13-μm CMOS process, the ROIC’s effective resolution is 17.0 bits at gain 1 and that of 14.6 bits at gain 128. The analog part draws the average current of 139.4 μA from 3-V supply, and 60.2 μA from a 1.8 V supply.본 논문에서는 고정밀 브리지 센서 센싱 시스템을 위한 에너지 효율이 높은 Read-out Integrated Circuit (read-out IC)를 제안한다. 저 잡음 Capacitively-Coupled Instrumentation Amplifier (CCIA)에 이은 고해상도 Discrete-time Delta-Sigma 변조기(DTΔΣΜ) 아날로그-디지털 변환기(ADC)를 구현하였다. 에너지 효율을 높이기 위해 IA 유형 중 에너지 효율이 가장 높은 CCIA를 선택하였다. CCIA는 브리지 센서의 작은 출력을 증폭할 수 있는 1 에서 128의 프로그래밍 가능한 전압 이득을 가진다. CCIA의 단점인 낮은 입력 임피던스를 보상하기 위해 Impedance Boosting Loop (IBL)을 적용하였다. 또한 CCIA에 센서 오프셋 제거 기술을 적용하여 브리지 센서의 저항 미스매치로 인한 오프셋을 제거 기능을 탑재하였으며 -350mV에서 350mV까지 브리지 센서 오프셋을 제거할 수 있다. Read-out IC의 출력 데이터 전송률은 12.8kHz로 설계하여 데이터를 빠르게 채고 나머지 시간 동안 센서와 read-out IC를 꺼서 센서의 전력 소비를 줄일 수 있도록 설계하였다. 일반적으로 브리지 센서 시스템은 12.8kHz보다 느리기 때문에 이것이 가능하다. 하지만, 일반적인 CCIA는 입력 임피던스 때문에 빠른 속도에서 설계가 불가능하다. 이를 해결하기 위해 demodulate 차핑을 앰프 내부가 아닌 시스템 차핑을 이용해 해결하였다. 1/f 노이즈를 억제하기 위해 시스템 레벨 차핑 및 상관 이중 샘플링(CDS) 기술이 사용되었다. 0.13μm CMOS 공정에서 구현된 read-out IC의 Effective Resolution (ER)은 전압 이득 1에서 17.0비트이고 전압 이득 128에서 14.6비트를 달성하였다. 아날로그 회로는 3 V 전원에서 139.4μA의 평균 전류를, 디지털 회로는 1.8 V 전원에서 60.2μA의 평균 전류를 사용한다.CHAPTER 1 INTRODUCTION 1 1.1 SMART DEVICES 1 1.2 SMART SENSOR SYSTEMS 4 1.3 WHEATSTONE BRIDGE SENSOR 5 1.4 MOTIVATION 8 1.5 PREVIOUS WORKS 10 1.6 INTRODUCTION OF THE PROPOSED SYSTEM 14 1.7 THESIS ORGANIZATION 16 CHAPTER 2 SYSTEM OVERVIEW 17 2.1 SYSTEM ARCHITECTURE 17 CHAPTER 3 IMPLEMENTATION OF THE CCIA 19 3.1 CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER 19 3.2 IMPEDANCE BOOSTING 22 3.3 SENSOR OFFSET CANCELLATION 25 3.4 AMPLIFIER OFFSET CANCELLATION 29 3.5 AMPLIFIER IMPLEMENTATION 32 3.6 IMPLEMENTATION OF THE CCIA 35 CHAPTER 4 INCREMENTAL ΔΣ ADC 37 4.1 INTRODUCTION OF INCREMENTAL ΔΣ ADC 37 4.2 IMPLEMENTATION OF INCREMENTAL ΔΣ MODULATOR 40 CHAPTER 5 SYSTEM-LEVEL DESIGN 43 5.1 DIGITAL FILTER 43 5.2 SYSTEM-LEVEL CHOPPING & TIMING 46 CHAPTER 5 MEASUREMENT RESULTS 48 6.1 MEASUREMENT SUMMARY 48 6.2 LINEARITY & NOISE MEASUREMENT 51 6.3 SENSOR OFFSET CANCELLATION MEASUREMENT 57 6.4 INPUT IMPEDANCE MEASUREMENT 59 6.5 TEMPERATURE VARIATION MEASUREMENT 63 6.6 PERFORMANCE SUMMARY 66 CHAPTER 7 CONCLUSION 68 APPENDIX A. 69 ENERGY-EFFICIENT READ-OUT IC FOR HIGH-PRECISION DC MEASUREMENT SYSTEM WITH IA POWER REDUCTION TECHNIQUE 69 BIBLIOGRAPHY 83 한글초록 87박

Architecture design of multiplexed incremental analog-to-digital converters

Analog-to-Digital Data Converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental data converters (IDCs) provide a solution for such measurement applications. Since IDCs are essentially delta-sigma converters with reset operation before each conversion, they retain most of the advantages of conventional [delta sigma] converters, and yet they are capable of offset-free and accurate conversion.Most of the previous research on incremental converters is for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this thesis, the operation and the performance ofIDCs in both frequency and time domain is analyzed. Design techniques for implementing multiplexed IDCs to convert narrow bandwidth ac signals are discussed too. It incorporates the operation principles, modulator topologies, digital filter design and signal-to-noise ratio optimization methodology. The theoretical analysis is verified by simulation results.Keywords: Incremental data converter, AD converter, decimation filte

A graphical method for determining the uniqueness of operating points in self-biasing circuits

In self-biasing circuits, designers often use feedbacks to reduce the power-supply sensitivity and minimize the effects of process and temperature variations. Many self-stabilized circuits are used in SOC circuits even when the SOC has a small amount of AMS content. It is well-known that these self-stabilized circuits are vulnerable to not starting-up correctly so start-up circuits are often included to prevent the circuit from getting stuck in an undesired stable operating point. Determining the uniqueness of an operating point in a circuit is challenging since circuit simulators only give a single operating point rather than all operating points. Moreover, this problem is very closely related to the mathematical problem of finding all solutions to a set of nonlinear equations. Both the mathematical and computer science communities recognize this as an open problem with no solution in sight. In circuits with multiple operating points, when a circuit simulator always gives the desired operating point throughout the design and verification process, there is little evidence that one or more undesired operating points even exist. In the semiconductor industry, designers use experience and intuition to identify start-up problems. Some self-stabilized circuits designed by trusted engineers unpredictably get stuck in an undesirable operating point. Engineers often attempt to verify start-up effectiveness with transient simulations. This approach is heuristic and time consuming. Moreover, multiple operating points may still exist in circuits. All circuits we have studied with known need for start-up circuits have a positive feedback loop (PFL) as part of the self-stabilization process. As a result, we made a conjecture that, A circuit is vulnerable to the multiple operating points problem only if the circuit has one or more Positive Feedback Loops. A graphical method for identifying positive feedback loops in analog circuits is presented for the purpose of identifying the stable equilibrium points. Firstly, since our method is based on graphical concepts, some key terminologies from graph theory will be reviewed. Secondly, Graphical models for key analog components are developed and then hierarchically used to obtain a graphical representation of an analog circuit. Thirdly, the concept of determining positive feedback loops from the small-signal resistive Directed, Weighted, Multi-Graph (DWM Graph) of a circuit will be addressed. The three-step process will be used to determine the positive feedback loops. Lastly, a method for breaking positive feedback loop and how to apply the homotopy method to create a return map for the positive feedback loop is introduced. By breaking the positive feedback loop in the circuit and applying break-loop homotopy method, it can determine the uniqueness of operating points in self-biasing circuits. Sample-and-hold circuit is wildly used in mixed-signal circuits such as data converters, filters etc. Thermal noise is often a design limitation in mixed-signal designs. Many literatures and analog textbooks state that the thermal noise voltage sampled on a capacitor is where k is Boltzmann constant, T is temperature and C is capacitance [21][24]. From the expression of thermal noise voltage, we can find that thermal noise is highly related to the capacitor values and independent of resistors. The only way to reduce thermal noise voltage is to increase the capacitance. However, a large capacitor increases the settling time and reduce sampling rate. Meanwhile, layout area and power dissipation will be increased. There is a tradeoff between settling time and accuracy. No literatures introduce a method for reducing thermal noise without increasing capacitance. Reducing noise on a sampling capacitor below may give designers opportunities for improving system performance. A method for reducing thermal noise voltage on a sampling capacitor dramatically below is introduced. In high resolution SAR ADC design, many papers state that the minimum capacitance of capacitor DAC is determined by the thermal noise limitation. This thermal noise limitation is kT/C where k is Boltzmann constant, T is temperature and C is the total capacitance of capacitor DAC. Moreover, they assume this is the input-referred noise for the whole ADC. However, this calculation ignores the noise from charge-redistribution mode completely. Meanwhile, no literatures introduce any method about numerical calculation of thermal noise from charge-redistribution mode of capacitor DAC of SAR ADC. A numerical calculation of thermal noise from charge-redistribution mode of capacitor DAC of SAR ADC is introduced

Low-Noise Energy-Efficient Sensor Interface Circuits

Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone. Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy. An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures. Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd

Efficient delta-sigma ADC for mobile audio applications based on a LabVIEW assisted architectural design flow

Questo lavoro di tesi è il risultato della fruttuosa collaborazione tra l’azienda multinazionale ST-Ericsson e il Dipartimento di Ingegneria dell’Informazione dell’Università di Pisa. ST-Ericsson è una delle aziende ”leader” nei mercati dei “modem“ e dei processori in banda base. Il gruppo di “mixed signal design“ nell’area di Zurigo (Svizzera) unitamente al gruppo basato a Bangalore (India) hanno, tra gli altri obbiettivi, la continua ricerca di soluzioni per migliorare l’efficienza ed il costo dei sotto-sistemi audio. Questa è stata quindi la base di lavoro per l’inizio di una collaborazione con l’accademia su tali temi. Lo studio è iniziato con una valutazione dello stato dell’arte dei “computer aided design tool” (CAD tool) per gli studi architetturali e per la validazione dei progetti dei convertitori delta-sigma sia in banda audio sia per applicazioni a larga ampiezza di banda, riscontrando una mancanza di flessibilità nell’area dei flussi per la scelta di architetture orientate al progetto. Sulla base di tali evidenze è stato sviluppato un nuovo “software” implementato in LabVIEW e finalizzato a guidare la scelta dei parametri di progetto di un convertitore analogico-digitale (ADC) delta-sigma. Tale “CAD tool” considera la minimizzazione dell’area di silicio già nella scelta dell’architettura lasciando al progettista la possibilità di implementare dei requisiti addizionali per la minimizzazione dell’area piuttosto che scegliere i parametri di progetto (coefficienti della risposta in frequenza) con il solo fine di ottenere le prestazioni desiderate. L’architettura della catena di “uplink” del processore in banda base è stata inoltre riprogettata e la funzionalità di alcuni blocchi è stata implementata nel ADC. Il controllo del guadagno, tradizionalmente effettuato da un amplificatore a guadagno variabile o “programmable gain amplifier” (PGA) attivato in corrispondenza degli attraversamenti dello zero rilevati da un “zero crossing detector” (ZCD), è stato inserito nell’anello di reazione del ADC attraverso un banco di condensatori selezionabili tramite controllo digitale. Gli effetti della commutazione del guadagno sul “dithering” e sulla traslazione del “idle-tone” sono state esaminati e sono state proposte delle soluzioni. Questo ha aperto alla possibilità di migliorare la qualità delle transizioni di guadagno attraverso un controllo a modulazione di larghezza dell’impulso o “Pulse Width Modulation” (PWM) che consente una variazione del guadagno e di conseguenza del segnale audio, molto più graduale rispetto a quanto avviene nelle soluzioni attualmente disponibili sul mercato. Infine un ADC in banda audio con area pari a 0.073 mm2 e consumo di corrente pari a 950 A da una tensione di alimentazione di 2.3 V, è stato realizzato in tecnologia CMOS 40nm. Il progetto è stato validato tramite la caratterizzazione sperimentale sia su un microchip di silicio a se’ stante contenente il solo ADC, sia sulla catena audio del processore in banda base G4860 che sta per essere adottato da Samsung per una prossima generazione di telefoni cellulari. Tra i principali obiettivi innovativi raggiunti si hanno: (i) Riduzione del 15% dell’area occupata dai condensatori commutati rispetto alle soluzioni di ADC riportati in letteratura con simili prestazioni, (ii) riduzione del 25% in area e del 30% in corrente nella catena di “uplink” audio sviluppata per un progetto GSM commerciale per mezzo dell’eliminazione sia del PGA che dello ZCD nel “front-end” audio, (iii) maggiore gradualità nel cambiamento del guadagno rispetto i dispositivi esistenti grazie ad una tecnica di controllo originale che è stata proposta per l’ottenimento di un brevetto da parte di ST-Ericsson

Continuous time input pipeline ADCs

Analog-to-digital converters (ADCs) convert analog continuous time signals into discrete time, digital format. One precondition that must be met for conventional nyquist rate ADCs is that the input signal must be suitably band-limited to an input bandwidth less than the nyquist frequency. This mandates expensive anti-alias filters which contribute to system noise and distortion degradation. By choosing an OSR of 2 and adopting simple linear phase filtering techniques, significant inherent anti-alias filtering is achieved, avoiding the need for an explicit anti-alias filter in many applications. Additionally the proposed continuous time input pipeline ADC eases a number of other challenges present in conventional switched capacitor ADCs:- sampled opamp noise folding, sampling distortion, reduced ADC area, switched-capacitor pipeline ADC input loading. Chapter 2 introduces the first continuous time input pipeline ADC in the literature. This ADC, while providing significant benefits, does not provide the inherent filtering. Chapter 3 presents the first continuous time input pipeline ADC with inherent anti-alias filtering