Comparisons & analyses of U.S. & global economic data & trends

Issued as final reportSRI Internationa

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Enabling hybrid process metrology in roll-to-roll nanomanufacturing: design of a tip-based tool for topographic sampling on flexible substrates

This work seeks to demonstrate the efficacy of a novel approach for topography measurement of nano-scale structures fabricated on a flexible substrate in a roll-to-roll (R2R) fashion. R2R manufactured products can be extremely cost competitive compared to more traditional, silicon wafer or glass panel based nanofabrication solutions, in addition to the unique and often desirable mechanical properties inherent to flexible substrates. As such, flexible nanomanufacturing is an area of immense research interest. However, despite the significant potential of these products for a variety of applications, developing manufacturing systems from lab-scale prototypes to pilot- or high volume manufacturing (HVM) has often proven both difficult and infeasibly expensive as research investment and achievable process yield limit advancement. One of the most significant capability gaps in current art, and roadblocks on the path towards adoption of R2R nanomanufacturing, is the lack of high-throughput, nanometer-scale metrology for process development, real-time control, and yield enhancement. This dissertation presents the design of a tip-based measurement tool implementing atomic force microscope (AFM) probes manufactured with a micro-electro-mechanical system (MEMS) approach to the challenge of sub-micron topography measurement which is also compatible with R2R manufacturing on flexible substrates. A proof-of-concept prototype tool with subsystems to regulate a flexible web, isolate and position the atomic force microscope probe, and measure features on the substrate, all coordinated by a real-time embedded control system, was designed and fabricated. The positioning subsystem was evaluated dynamically to ensure initial design requirements were met, and stationery, step-and-scan results were presented. However, to wholly meet this extent need for in-line R2R metrology, a system capable of atomic force microscope scanning despite a continuous, non-zero substrate velocity is required - any regular stoppage of the web in a R2R process all but dooms economically viable production throughput. Refinement and redesign of the proof-of-concept tool was driven by new system requirements to meet this goal, in addition to lessons learned from the initial prototype. Improvements focused on upgrading the web handling spindle design and mechatronics, tool power electronics, moving structures, and control algorithms used for high-speed synchronous positioning of the atomic force microscope and web. The culmination of this work will serve to introduce a new measurement framework which may be used to accelerate and enable future research in R2R manufacturing of nanofeatured products.Mechanical Engineerin

Empirical Analysis of Electron Beam Lithography Optimization Models from a Pragmatic Perspective

Electron Beam (EB) lithography is a process of focussing electron beams on silicon wafers to design different integrated circuits (ICs). It uses an electron gun, a blanking electrode, multiple electron lenses, a deflection electrode, and control circuits for each of these components. But the lithography process causes critical dimension overshoots, which reduces quality of the underlying ICs. This is caused due to increase in beam currents, frequent electron flashes, and reducing re-exposure of chip areas. Thus, to overcome these issues, researchers have proposed a wide variety of optimization models, each of which vary in terms of their qualitative & quantitative performance. These models also vary in terms of their internal operating characteristics, which causes ambiguity in identification of optimum models for application-specific use cases. To reduce this ambiguity, a discussion about application-specific nuances, functional advantages, deployment-specific limitations, and contextual future research scopes is discussed in this text. Based on this discussion, it was observed that bioinspired models outperform linear modelling techniques, which makes them highly useful for real-time deployments. These models aim at stochastically evaluation of optimum electron beam configurations, which improves wafer’s quality & speed of imprinting when compared with other models. To further facilitate selection of these models, this text compares them in terms of their accuracy, throughput, critical dimensions, deployment cost & computational complexity metrics. Based on this discussion, researchers will be able to identify optimum models for their performance-specific use cases. This text also proposes evaluation of a novel EB Lithography Optimization Metric (EBLOM), which combines multiple performance parameters for estimation of true model performance under real-time scenarios. Based on this metric, researchers will be able to identify models that can perform optimally with higher performance under performance-specific constraints

Internationalisation of Innovation: Why Chip Design Moving to Asia

This paper will appear in International Journal of Innovation Management, special issue in honor of Keith Pavitt, (Peter Augsdoerfer, Jonathan Sapsed, and James Utterback, guest editors), forthcoming. Among Keith Pavitt's many contributions to the study of innovation is the proposition that physical proximity is advantageous for innovative activities that involve highly complex technological knowledge But chip design, a process that creates the greatest value in the electronics industry and that requires highly complex knowledge, is experiencing a massive dispersion to leading Asian electronics exporting countries. To explain why chip design is moving to Asia, the paper draws on interviews with 60 companies and 15 research institutions that are doing leading-edge chip design in Asia. I demonstrate that "pull" and "policy" factors explain what attracts design to particular locations. But to get to the root causes that shift the balance in favor of geographical decentralization, I examine "push" factors, i.e. changes in design methodology ("system-on-chip design") and organization ("vertical specialization" within global design networks). The resultant increase in knowledge mobility explains why chip design - that, in Pavitt's framework is not supposed to move - is moving from the traditional centers to a few new specialized design clusters in Asia. A completely revised and updated version has been published as: " Complexity and Internationalisation of Innovation: Why is Chip Design Moving to Asia?," in International Journal of Innovation Management, special issue in honour of Keith Pavitt, Vol. 9,1: 47-73.

A CAPACITY MODEL FOR RESEARCH BASED GOVERNMENT MANUFACTURING SYSTEMS

Manufacturing systems take longer than necessary to be designed and implemented, hence the greater developmental cost. A class of manufacturing systems exist which would benefit from the concepts of reverse engineering, to reduce lead times for establishing critical manufacturing capabilities essential to national safety and security. There is a need to reverse engineer these manufacturing systems as no current system and/or body of knowledge exists. Manufacturing systems vary in their ability to deliver products in an efficient and reliable manner and hence the variability in national readiness. Presently the design of manufacturing systems for some critical operations ranges from an educated trial and error process to duplicating from documentation and professional expertise. The literature search highlights the non-existence of a current systematic operational reverse engineering model that could be the standard for designing manufacturing systems. One of the main constraints in the manufacturing is that the time for production is limited and denoted by time available (TA). The time to finish (TF) is the time needed to complete the manufacturing operations in a facility so that the entire quantity demanded is produced, from start to end, in the production line. If the TF is less than the TA there is sufficient capacity to meet the demand. Literature search indicates that no study has been conducted to compute the TF. Further, it also indicates that no study has been carried out focusing on the vi impact of variations and disruptions at the design stage, even though these topics are covered in analysis of existing operational systems. The algorithms and mathematical model were developed. The model will compute the exact TF taking into account variation, disruption and flow issues. The equation for TF was developed. The model to be designed is validated using information from a government manufacturing system

Molecular machinery and manufacturing with applications to computation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Architecture, 1991.Vita.Includes bibliographical references (p. 469-487).by K. Eric Drexler.Ph.D

Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

Siirretty Doriast