Sub-micron technology development and system-on-chip (Soc) design - data compression core

Data compression removes redundancy from the source data and thereby increases storage capacity of a storage medium or efficiency of data transmission in a communication link. Although several data compression techniques have been implemented in hardware, they are not flexible enough to be embedded in more complex applications. Data compression software meanwhile cannot support the demand of high-speed computing applications. Due to these deficiencies, in this project we develop a parameterized lossless universal data compression IP core for high-speed applications. The design of the core is based on the combination of Lempel-Ziv-Storer-Szymanski (LZSS) compression algorithm and Huffman coding. The resulting IP core offers a data-independent throughput that can process a symbol in every clock cycle. The design is described in parameterized VHDL code to enable a user to make a suitable compromise between resource constraints, operation speed and compression saving, so that it can be adapted for any target application. In implementation on Altera FLEX10KE FPGA device, the design offers a performance of 800 Mbps with an operating frequency of 50 MHz. This IP core is suitable for high-speed computing applications or for storage systems

Design verification and performance analysis of Serial AXI Links in Broadcom System-on-Chip

Design verification is an essential step in the development of any product. Also referred to as qualification testing, design verification ensures that the product as designed is the same as the product as intended. In this project, design verification and performance analysis of Thin Advanced Extensible Interface Links (T-AXI) is conducted on a Broadcom’s SoC (System on Chip). T-AXI is a Broadcom’s proprietary bus that interfaces all the subsystems on the System-onchip (SoC) to the system memory. Test cases are developed to verify the functionality of the T-AXI and performance verification is implemented using scenarios derived from real world examples. A Field Programmable Gate Array (FPGA) is used to emulate the SoC design and C programming is used to write the test cases. The test results verify the T-AXI functionality and the performance analysis supports the theoretical calculations

A parallel implementation of the confined–unconfined aquifer system model for subglacial hydrology: design, verification, and performance analysis (CUAS-MPI v0.1.0)

Abstract. The subglacial hydrological system affects (i) the motion of ice sheets through sliding, (ii) the location of lakes at the ice margin, and (iii) the ocean circulation by freshwater discharge directly at the grounding line or (iv) via rivers flowing over land. For modeling this hydrology system, a previously developed porous-media concept called the confined–unconfined aquifer system (CUAS) is used. To allow for realistic simulations at the ice sheet scale, we developed CUAS-MPI, an MPI-parallel C/C++ implementation of CUAS (MPI: Message Passing Interface), which employs the Portable, Extensible Toolkit for Scientific Computation (PETSc) infrastructure for handling grids and equation systems. We validate the accuracy of the numerical results by comparing them with a set of analytical solutions to the model equations, which involve two types of boundary conditions. We then investigate the scaling behavior of CUAS-MPI and show that CUAS-MPI scales up to 3840 MPI processes running a realistic Greenland setup on the Lichtenberg HPC system. Our measurements also show that CUAS-MPI reaches a throughput comparable to that of ice sheet simulations, e.g., the Ice-sheet and Sea-level System Model (ISSM). Lastly, we discuss opportunities for ice sheet modeling, explore future coupling possibilities of CUAS-MPI with other simulations, and consider throughput bottlenecks and limits of further scaling. </jats:p

Fast Simulation of Wireless Systems

Cellular communication systems, sometimes referred to as wireless systems , are complex enough to require simulation in the design, verification and performance analysis stages. Simulations of wireless models are computationally intensive due the nature of the problem, but even more so due to the size of the systems of interest. This work proposes the evaluation and development of techniques to accelerate wireless simulations. As an initial effort, we evaluate the effectiveness of methods that may result in substantial reduction of run time in sequential simulations. In this stage, we study the application of algorithms for the N-body problem to the computation of signal to noise ratios and also the acceleration of the continuous part of the model by making discrete jumps in time, rather than time-stepping. As the next natural step in minimizing execution time is to construct models for parallel execution, we propose to investigate the suitability of strategies for problem partitioning..