13 research outputs found

    Biomedical Engineering

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    Biomedical engineering is currently relatively wide scientific area which has been constantly bringing innovations with an objective to support and improve all areas of medicine such as therapy, diagnostics and rehabilitation. It holds a strong position also in natural and biological sciences. In the terms of application, biomedical engineering is present at almost all technical universities where some of them are targeted for the research and development in this area. The presented book brings chosen outputs and results of research and development tasks, often supported by important world or European framework programs or grant agencies. The knowledge and findings from the area of biomaterials, bioelectronics, bioinformatics, biomedical devices and tools or computer support in the processes of diagnostics and therapy are defined in a way that they bring both basic information to a reader and also specific outputs with a possible further use in research and development

    Energy Efficient Wireless Circuits for IoT in CMOS Technology

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    The demand for efficient and reliable wireless communication equipment is increasing at a rapid pace. The demand and need vary between different technologies including 5G and IoT. The Radio Frequency Integrated Circuits (RFIC) designers face challenges to achieve higher performance with lower power resources. Although advances in Complementary Metal-Oxide-Semiconductor (CMOS) technology has help designers, challenges still exist. Thus, novel and new ideas are welcome in RFIC design. In this dissertation, many ideas are introduced to improve efficiency and linearity for wireless receivers dedicated to IoT applications. A low-power wireless RF receiver for wireless sensor networks (WSN) is introduced. The receiver has improved linearity with incorporated current-mode circuits and high-selectivity filtering. The receiver operates at a 900 MHz industrial, scientific and medical (ISM) band and is implemented in 130 nm CMOS technology. The receiver has a frequency multiplication mixer, which uses a 300 MHz clock from a local oscillator (LO). The local oscillator is implemented using vertical delay cells to reduce power consumption. The receiver conversion gain is 40 dB and the receiver noise figure (NF) is 14 dB. The receiver IIP3 is −6 dBm and the total power consumption is 1.16 mW. A wireless RF receiver system suitable for Internet-of-Things (IoT) applications is presented. The system can simultaneously harvest energy from out-of-band (OB) blockers with normal receiver operation; thus, the battery life for IoT applications can be extended. The system has only a single antenna for simultaneous RF energy harvesting and wireless reception. The receiver is a mixer-first quadrature receiver designed to tolerate large unavoidable blockers. The system is implemented in 180 nm CMOS technology and operates at 900 MHz industrial, scientific and medical (ISM) band. The receiver gain is 41.5 dB. Operating from a 1 V supply, the receiver core consumes 430 µW. This power can be reduced to 220 µW in the presence of a large blocker (≈ 0 dBm) by the power provided by the blocker RF energy harvesting where the power conversion efficiency (PCE) is 30%. Finally, a highly linear energy efficient wireless receiver is introduced. The receiver architecture is a mixer-first receiver with a Voltage Controlled Oscillator (VCO) based amplifier incorporated as baseband amplifier. The receiver benefits from the high linearity of this amplifier. Moreover, novel clock recycling techniques are applied to make use of the amplifier’s VCOs to clock the mixer circuit and to improve power consumption. The system is implemented in 130 nm CMOS technology and operates at 900 MHz ISM band. The receiver conversion gain is 42 dB and the power consumption is 2.9 mW. The out-of-band IIP3 is 6 dBm. All presented systems and circuits in this dissertation are validated and published in various IEEE journals and conferences

    Design Considerations of a Sub-50 {\mu}W Receiver Front-end for Implantable Devices in MedRadio Band

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    Emerging health-monitor applications, such as information transmission through multi-channel neural implants, image and video communication from inside the body etc., calls for ultra-low active power (<50μ{\mu}W) high data-rate, energy-scalable, highly energy-efficient (pJ/bit) radios. Previous literature has strongly focused on low average power duty-cycled radios or low power but low-date radios. In this paper, we investigate power performance trade-off of each front-end component in a conventional radio including active matching, down-conversion and RF/IF amplification and prioritize them based on highest performance/energy metric. The analysis reveals 50Ω{\Omega} active matching and RF gain is prohibitive for 50μ{\mu}W power-budget. A mixer-first architecture with an N-path mixer and a self-biased inverter based baseband LNA, designed in TSMC 65nm technology show that sub 50μ{\mu}W performance can be achieved up to 10Mbps (< 5pJ/b) with OOK modulation.Comment: Accepted to appear on International Conference on VLSI Design 2018 (VLSID

    Radio frequency front end receiver blocks with ultra low supply voltage and low power dissipation for Zigbee applications

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    Portable wireless devices have been the heat of demands in recent years for many applications such as Wireless Sensor Network (WSN) which requires low power consumption since these devices are commonly powered up by battery. One way to reduce circuit power consumption is to lower the supply voltage or DC current of the circuit. Continuous modern technology scaling with a proportional supply voltage reduction outlays a challenge in designing Radio Frequency (RF) circuits. In fact, the recent supply voltage and power consumption for mixer have been saturated at around 0.8V and 1mW respectively. Direct conversion receiver (DCR) is the preferred choice of low power adaptation for the receiver front-end. The most common topologies for mixer are Gilbert cell, folded cascode and current bleeding mixer. However, these architectures still require high supply voltage to operate. The proposed architecture combines the current bleeding technique and folded structure to realize the operation at ultra-low supply voltage of 0.5V while enhancing the isolation between Local Oscillator (LO) and RF ports. This mixer exhibits a measured conversion gain of 11dB at the radio frequency (RF) of 2.4GHz, an input third-order intercept point (IIP3) of -0.4dBm and a LO-RF isolation measured to 60 dB and the DC power consumption is 850μW. This research also includes the design and analysis of current bleeding mixer topology adapting forward body bias technique coupled with the integration of an inductor at the gate of the NMOS bleeding transistor to increase the conversion gain without additional DC power consumption. The measured conversion gain and IIP3 of this mixer is 13dB and -0.5dBm respectively and only consume DC power of 480μw and operates at 0.35V of supply voltage. Integrated LNA-Mixer is investigated in this thesis which focuses on ultra-low voltage and low power implementation. This integrated chip features a simulated conversion gain of 20.3dB at the radio frequency (RF) of 2.4GHz, an input third-order intercept point (IIP3) of -10.3dBm and Noise Figure (NF) is at 7.2dB. The dc power consumption is 950μw while working at the supply voltage of 0.5V. The circuits are designed such that the critical transistors operate at optimum transconductance to meet the low power requirement of ZigBee applications. All circuits were fabricated using CMOS 0.13um technology and measurement was performed on die samples. As a conclusion, the ultra-low voltage and low-power techniques used in this research meets the requirement for ZigBee applications while working at supply voltage of 0.5V and 0.35V with power dissipation of less than 1mW

    Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

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    Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter

    Design of ultra-low voltage 0.5V CMOS current bleeding mixer

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    This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4GHz frequency band. It introduces and discusses a modified CMOS based current bleeding mixer topology adopting a combination of NMOS current bleeding transistor, with a PMOS Local Oscillator (LO) switching stage and integrated inductors to achieve ultra-low voltage headroom operation at 0.5V. This mixer is simulated and verified in 0.13µm standard CMOS technology. The result shows a conversion gain (CG) of 11.84dB, 1dB compression point (P1dB) at -14.36dBm, third-order intercept point (IIP3) of -5dBm and a noise figure (NF) of 15dB and with a power consumption of 930µW

    Design of Low-Power Short-Distance Transceiver for Wireless Sensor Networks

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    Ph.DDOCTOR OF PHILOSOPH

    Analysis and design of low power CMOS ultra wideband receiver

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    This research concentrates on the design and analysis of low power ultra wideband receivers for Multiband Orthogonal Frequency Division Multiplexing systems. Low power design entails different performance tradeoffs, which are analyzed. Relationship among power consumption, achievable noise figure and linearity performance including distortion products (cross-modulation, inter-modulation and harmonic distortion) are derived. From these relationships, circuit design proceeds with allocation of gain among different sub circuit blocks for power optimum system. A power optimum RF receiver front-end for MB-OFDM based UWB systems is designed that covers all the MB-OFDM spectrum between 3.1 GHZ to 9.6 GHZ. The receiver consists of a low-noise amplifier, down-converter, channel select filter and programmable gain amplifier and occupies only 1mm 2 in 0.13um CMOS process. Receiver consumes 20 mA from a 1.2 V supply and has the measured gain of 69db, noise figure less than 6 dB and input IIP 3 of -6 dBm
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