Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter

Reconfigurable RF Front End Components for Multi-Radio Platform Applications

The multi-service requirements of the 3G and 4G communication systems, and their backward compatibility requirements, create challenges for the antenna and RF front-end designs with multi-band and wide-band techniques. These challenges include: multiple filters, which are lossy, bulky, and expensive, are needed in the system; device board size limitation and the associated isolation problems caused by the limited space and crowd circuits; and the insertion loss issues created by the single-pole-multi-through antenna switch. As will be shown, reconfigurable antennas can perform portions of the filter functions, which can help solve the multiple filters problem. Additionally, reconfigurable RF circuits can decrease the circuit size and output ports, which can help solve board size limitation, and isolation and antenna switch insertion loss issues. To validate the idea that reconfigurable antennas and reconfigurable RF circuits are a viable option for multi-service communication system, a reconfigurable patch antenna, a reconfigurable monopole antenna, and a reconfigurable power amplifier (PA) have been developed. All designs adapt state-of-the-art techniques. For the reconfigurable antenna designs, an experiment demonstrating its advantages, such as jamming signal resistance, has been performed. Reconfigurable antennas provide a better out-ofoperating- band noise performance than the multi-band antennas design, decreasing the need for filters in the system. A full investigation of reconfigurable antennas, including the single service reconfigurable antenna, the mixed signal service reconfigurable antenna, and the multi-band reconfigurable antenna, has been completed. The design challenges, which include switches investigation, switches integration, and service grouping techniques, have been discussed. In the reconfigurable PA portion, a reconfigurable PA structure has first been demonstrated, and includes a reconfigurable output matching network (MN) and a reconfigurable die design. To validate the proposed reconfigurable PA structure, a reconfigurable PA for a 3G cell phone system has been designed with a multi-chip module technique. The reconfigurable PA structure can significantly decrease the real-estate, cost, and complexity of the PA design. Further, by decreasing the number of output ports, the number of poles for the antenna switch will be decreased as well, leading to an insertion loss decrease

Design of reconfigurable multi-mode RF circuits

Wireless communication systems and devices have been developing at a much faster pace in the past few years. With the introduction of new applications and services and the increasing demand for higher data rate comes the need for new frequency bands and new standards. One critical issue for next generation wireless devices is how to support all of the existing and emerging bands while not increasing the cost and power consumption. A feasible solution is the concept of the software-defined radio where a single receiver can be reconfigured to operate in different modes, each of which supports one or several bands and/or standards. To implement such a reconfigurable receiver, reconfigurable RF building blocks, such as the LNA, mixer, VCO, etc., are required. This dissertation focuses on two key blocks: the low noise amplifier (LNA) and the voltage controlled oscillator (VCO). First the design, modeling and characterization of a multi-tap transformer are discussed. Simple mathematical calculations are utilized to estimate the inductances and coupling coefficients from the physical parameters of a multi-tap transformer. The design method is verified with several designed multi-tap transformers that are characterized up to 10 GHz using Momentum simulation results. The effect of switch loss on a switched multi-tap transformer is explored and a broadband lumped-element model of the multi-tap transformer is also proposed. Next a reconfigurable multimode LNA capable of single-band, concurrent dual-band, and ultra-wideband operation is presented. The multimode operation is realized by incorporating a switched multi-tap transformer into the input matching network of an inductively degenerated common source amplifier. The proposed LNA achieves single band matching at 2.8, 3.3, and 4.6 GHz; concurrent dual-band matching at 2.05 and 5.65 GHz; and ultra-wideband matching from 4.3 to 10.8 GHz. The chip was fabricated in a 0.13 m CMOS process, and occupies an area of 0.72 mm2, and has a power dissipation of 6.4 mW from a 1.2-V supply. Finally, a triple-mode VCO using a transformer-based 4th order tank with tunable transconductance cells coupling the primary and secondary inductor is introduced. The tank impedance can be re-shaped by the transconductance cells through the tuning of their biasing currents. With the control of biasing current, VCO is configured in three modes, capable of generating a single frequency in 3- and 5- GHz bands, respectively, and two frequencies in both 3- and 5- GHz bands simultaneously. The triple-mode VCO was fabricated in a 0.13 μm CMOS process, occupies an area of 0.16 mm2, and dissipates 5.6 mW from a 1.2-V supply

Ultra-low power RF receiver based on double-gate CMOS FinFET technology

In this research, design approaches and methodologies were presented to realize the ultra-low power RF receiver front-end circuits. Moderate inversion operation was explored as a possible method of reducing power consumption along with the use of low supply voltage. The research is firstly concentrated on passive and active devices modeling. One of the most commonly used passive devices is on-chip inductor. On-chip spiral inductor model was developed firstly. Compared to the model developed by others, this model can predict the behavior of the inductors with different structural parameters over a board frequency range (from 0.1 to 10 GHz). Then the SOI varactor model was developed based on our measurement and extraction.Besides the passive devices modeling, a new most promising MOSFET candidate, FinFET, was characterized at GHz frequency range. Based on the measurement results, we found the FinFET transistors did have superior performance over bulk-Si CMOS technology. And an RF circuit model of FinFET was developed followed that, which was published in Electronics Letters. To my best knowledge, this was the first RF FinFET model published world wide at that time. It provides the basic idea about how to model this new structure MOSFET.Based on the passive and active device models developed, Global Positioning System (GPS) receiver front end circuits were designed and measured. Comparing to the previous designs with the same constrains, the ultra-low power GPS receiver building block circuits in this research have much less power consumption than the best design published before

Preliminary candidate advanced avionics system for general aviation

An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered

An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking

A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage LNA, quadrature oscillators, and quadrature mixers. It exhibits an order of magnitude lower power consumption than the best previously published work. The system has a measured gain of 42 dB, a noise figure of 8.6 dB, and an oscillator phase noise of -113.8 dBc/Hz at a 1 MHz offset while consuming a maximum of 580 μW of power and requiring no external components