Equation-based hierarchical optimization of a pipeline ADC

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (leaves 62-64).In system design, allocation of circuit resources like power and noise budget is a difficult problem. It is difficult to know the optimal distribution of resources because the performance space of each component is not fully characterized. This uncertainty results in an iterative approach with frequent re-design of circuit blocks for different distribution schemes. Equation-based optimization has been shown effective and time efficient in circuit design, but is impractical for systems due to the large number of variables resulting in long solve times. This work shows an equation-based hierarchical optimization strategy suitable for design in deeply scaled CMOS processes. Because it is a hierarchical methodology, it scales gracefully to systems that are much larger than can be handled by known optimization methods. This thesis matches flat and hierarchical optimizations of a 10-stage pipeline ADC in a 0.18-um process. A pipeline ADC was chosen because it is a system small enough to be handled by a flat optimization, yet large enough to be approached with a hierarchical methodology. This allows a quantitative comparison of the computation resources required by each strategy. In this approach, equation-based optimizations generate the Pareto-optimal surfaces of each pipeline stage. Exploiting the surfaces' gentle nature and amenability to low-order equation fits, they are abstracted to higher levels as representations of the circuit block. Thus, resources are allocated at the system level (such as power dissipation, noise budget, gain, etc.) very rapidly and very efficiently using familiar equation-based optimization strategies. In the end we demonstrate an optimization strategy that takes 25x less time to allocate resources than a traditional, flat methodology.by Tania Khanna.S.M

Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 107-110).Design of modern mixed signal integrated circuits is becoming increasingly difficult. Continued MOSFET scaling is approaching the global power dissipation limits while increasing transistor variability, thus requiring careful allocation of power and area resources to achieve increasingly more aggressive performance specifications. In this tightly constrained environment traditional iterative system-to-circuit redesign loop, is becoming inefficient. With complex system architectures and circuit specifications approaching technological limits of the process employed, the designers have less room to margin for the overhead of strict system and circuit design interdependencies. Severely constrained modern mixed IC design can take many iterations to converge in such a design flow. This is an expensive and time consuming process. The situation is particularly acute in high-speed links. As an important building block of many systems (high speed I/O, on-chip communication, ...) power efficiency and area footprint are of utmost importance. Design of these systems is challenging in both system and circuit domain. On one hand system architectures are becoming increasingly complex to provide necessary performance increase. On the other, circuit implementation of these increasingly complicated systems is difficult to achieve under tight power and area budget. To bridge this gap between system and circuit design, we formulate a circuit-to-system optimization-driven framework. It is an equation-based description, powered by a human designer. Provided with equation-based model we use fast optimization tools to quickly scout the available design space. Presence of a designer in the flow is invaluable resource enabling significant saving by simplifying the models to capture only the relevant information and constraining the search space to areas where meaningful solutions might be expected to be found.(cont) Thus, the computational effort overhead that plagues the simulation-based design space exploration and design optimization is greatly reduced. The flow is powered by a signomial optimization engine. The key challenge is to bring, from the modeling point of view, very different problems such as circuit design and system design into the realm of an optimization engine that can solve them jointly, thus breaking the re-design loop or at least cutting it shorter. Relying on signomial programming is necessary in order to accurately model all the necessary phenomenons that arise in electrical circuits and at system level. For example, defining regions of operation of transistors under polarization conditions can not be modeled accurately with simpler type of equations. Similarly, calculating the effect of filtering to a signal also requires possibility to handle signomial equations. Thus, signomial programming is necessary yet not fully explored and finding suitable formulation might take some experimenting as we will see in this thesis. Signomial programming, as a general non-convex optimization problem, is still an active research area. Most of the solutions proposed so far involve local convexification of the problem in addition to branch & bound type of search. Furthermore, most of the non-convex problems are solved for one particular system of equations, and general methodology that is reliable and efficient is not known. Thus, a big part the work to be presented in this thesis is detailing how to construct a system formulation that the optimization engine can solve efficiently and reliably. We tested different formulations and their performance measured in terms of parsing and solving speed and accuracy. From these tests we motivate and explain how a series of transformations we introduce improve our formulation and arrive to a well-behaved and reliable form. We show how to apply our design flow in high-speed link design.(cont) By restructuring the traditional design flow we derive system and circuit abstractions. These sub-problems are interfaced through a set of well defined interface variables, which enables code level separation of problem descriptions, thus building a modular and easy to read and maintain system and circuit model. Finally we develop a set of scripts to automate formulating parametrized system level description. We explain how our transformations influence the speed of this process as well as the size of the model produced.by Ranko Sredojević.S.M

Digital assistance design for analog systems : digital baseband for outphasing power amplifiers

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 145-150).Digital assistance is among many aspects that can be leveraged to help analog/mixed-signal designers keep up with the technology scaling. It usually takes the form of predistorter or compensator in an analog/mixed-signal system and helps compensate the nonidealities in the system. Digital assistance takes advantage of the process scaling with faster speed and a higher level of integration. When a digital system is co-optimized with system modeling techniques, digital assistance usually becomes a key enabling block for the high performance of the overall system. This thesis presents the design of digital assistances through the digital baseband design for outphasing power amplifiers. In the digital baseband design, this thesis conveys two major points: the importance of the use of the reduced-complexity system modeling techniques, and the communications between hardware design and system modeling. These points greatly help the success in the design of the energy-efficient baseband. The first part of the baseband design is to realize the nonlinear signal processing unit required by the modulation scheme. Conventional approaches of implementing this functionality do not scale well to meet the throughput, area and energy-efficiency targets. We propose a novel fixed-point piece-wise linear approximation technique for the nonlinear function computations involved in the signal processing unit. The new technique allows us to achieve an energy and area-efficient design with a throughput of 3.4Gsamples/s. Compared to the projected previous designs, our design shows 2x improvement in energy-efficiency and 25x in area-efficiency. The second part of the baseband design devotes to the nonlinear compensator design, aiming to improve the linearity performance of the outphasing power amplifier. We first explore the feasibility of a working compensator by use of an off-line iterative solving scheme. With the confirmation that a compensator does exist, we analyze the structure of the nonlinear baseband-equivalent PA system and create a dynamical real-time compensator model. The resulting compensator provides the overall PA system with around 10dB improvement in ACPR and up to 2.5% in EVM.by Yan Li.Ph.D

Energy-efficient analog-to-digital conversion for ultra-wideband radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 207-222).In energy constrained signal processing and communication systems, a focus on the analog or digital circuits in isolation cannot achieve the minimum power consumption. Furthermore, in advanced technologies with significant variation, yield is traditionally achieved only through conservative design and a sacrifice of energy efficiency. In this thesis, these limitations are addressed with both a comprehensive mixed-signal design methodology and new circuits and architectures, as presented in the context of an analog-to-digital converter (ADC) for ultra-wideband (UWB) radio. UWB is an emerging technology capable of high-data-rate wireless communication and precise locationing, and it requires high-speed (>500MS/s), low-resolution ADCs. The successive approximation register (SAR) topology exhibits significantly reduced complexity compared to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network enable the high-speed operation. Finally, only a small amount of redundancy, with negligible power penalty, dramatically improves the yield of the highly parallel ADC in deep sub-micron CMOS.by Brian P. Ginsburg.Ph.D