The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology

This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves > 18 dB conversion gain, a flat noise figure < 5.5 dB from 500 MHz to 7 GHz, IIP2 = +20 dBm and IIP3 = -3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than 0.01 mm2 in 65 nm CMOS

Early Days of SIS Receivers

The modern era of millimeter and submillimeter spectral line observations and interferometry started at end of the 1979 with the invention of the Superconductor-Insulator-Superconductor (SIS) mixer. Tom Phillips co-invented this device while working at Bell Telephone Labs (BTL) in Murray Hill, NJ. His group built the first astronomically useful SIS heterodyne receiver which was deployed on the Leighton 10.4 m telescope at the Caltech Owens Valley Radio Observatory (OVRO) in the same year. Tom Phillips joined the Caltech faculty in the early 1980s where his group continues to lead the way in developing state-of-the-art SIS receivers throughout the millimeter and submillimeter wavelength bands. The rapid progress in millimeter and submillimeter astronomy during 1980s required developments on many fronts including the theoretical understanding of the device physics, advances in device fabrication, microwave and radio frequency (RF) circuit design, mixer block construction, development of wideband low-noise intermediate frequency (IF) amplifiers and the telescopes used for making the observations. Many groups around the world made important contributions to this field but the groups at Caltech and the Jet Propulsion Laboratory (JPL) under the leadership of Tom Phillips made major contributions in all of these areas. The end-to-end understanding and developments from the theoretical device physics to the astronomical observations and interpretation has made this group uniquely productive

Gain Stabilization of a Submillimeter SIS Heterodyne Receiver

We have designed a system to stabilize the gain of a submillimeter heterodyne receiver against thermal fluctuations of the mixing element. In the most sensitive heterodyne receivers, the mixer is usually cooled to 4 K using a closed-cycle cryocooler, which can introduce ~1% fluctuations in the physical temperature of the receiver components. We compensate for the resulting mixer conversion gain fluctuations by monitoring the physical temperature of the mixer and adjusting the gain of the intermediate frequency (IF) amplifier that immediately follows the mixer. This IF power stabilization scheme, developed for use at the Submillimeter Array (SMA), a submillimeter interferometer telescope on Mauna Kea in Hawaii, routinely achieves a receiver gain stability of 1 part in 6,000 (rms to mean). This is an order of magnitude improvement over the typical uncorrected stability of 1 part in a few hundred. Our gain stabilization scheme is a useful addition to SIS heterodyne receivers that are cooled using closed-cycle cryocoolers in which the 4 K temperature fluctuations tend to be the leading cause of IF power fluctuations.Comment: 7 pages, 6 figures accepted to IEEE Transactions on Microwave Theory and Technique

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

A 0.8 V T Network-Based 2.6 GHz Downconverter RFIC

A 2.6 GHz downconverter RFIC is designed and implemented using a 0.18 μm CMOS standard process. An important goal of the design is to achieve the high linearity that is required in WiMAX systems with a low supply voltage. A passive T phase-shift network is used as an RF input stage in a Gilbert cell to reduce supply voltage. A single supply voltage of 0.8 V is used with a power consumption of 5.87 mW. The T network-based downconverter achieves a conversion gain (CG) of 5 dB, a single-sideband noise figure (NF) of 16.16 dB, an RF-to-IF isolation of greater than 20 dB, and an input-referred third-order intercept point (IIP3) of 1 dBm when the LO power of -13 dBm is applied

A wideband high-linearity RF receiver front-end in CMOS

This paper presents a wideband high-linearity RF receiver-front-end, implemented in standard 0.18 /spl mu/m CMOS technology. The design employs a noise-canceling LNA in combination with two passive mixers, followed by lowpass-filtering and amplification at IF. The achieved bandwidth is >2 GHz, with a noise figure of 6.5 dB, +1 dBm IIP/sub 3/, +34.5 dBm IIP/sub 2/ and <50 kHz 1/f-noise corner frequency

A Wideband Inductorless CMOS Front-End for Software Defined

The number of wireless communication links is witnessing tremendous growth and new standards are being introduced at high pace. These standards heavily rely on digital signal processing, making CMOS the first technology of choice. However, RF CMOS circuit development is costly and time consuming due to mask costs and design iterations. This pleads for a Software Defined Radio approach, in which one piece of flexible radio hardware is re-used for different applications and standards, downloadable and under software control. To the best of our knowledge, little work has been done in this field based on CMOS technology. Recently, a bipolar downconverter front-end has been proposed [1]. In CMOS, only wideband low-noise amplifiers have been proposed, and some CMOS tuner ICs for satellite reception (which have less stringent noise requirements because they are preceded by an outdoor low-noise converter). This paper presents a wideband RF downconverter frontend in 0.18 um CMOS (also published in [2]), designed in the context of a research project exploring the feasibility of software defined radio, using a combined Bluetooth/WLAN receiver as a vehicle. Usually, RF receivers are optimised for low power consumption. In contrast, we have taken the approach to optimise for flexibility. The paper discusses the main system and circuit design choices, and assesses the achievable performance via measurements on a front-end implemented in 0.18um CMOS. The flexible design achieves a 0.2-2.2 GHz -3 dB bandwidth, a gain of 25 dB with 6 dB noise figure and +1 dBm IIP3

A 275–425-GHz Tunerless Waveguide Receiver Based on AlN-Barrier SIS Technology

We report on a 275–425-GHz tunerless waveguide receiver with a 3.5–8-GHz IF. As the mixing element, we employ a high-current-density Nb–AlN–Nb superconducting–insulating– superconducting (SIS) tunnel junction. Thanks to the combined use of AlN-barrier SIS technology and a broad bandwidth waveguide to thin-film microstrip transition, we are able to achieve an unprecedented 43% instantaneous bandwidth, limited by the receiver's corrugated feedhorn. The measured double-sideband (DSB) receiver noise temperature, uncorrected for optics loss, ranges from 55 K at 275 GHz, 48 K at 345 GHz, to 72 K at 425 GHz. In this frequency range, the mixer has a DSB conversion loss of 2.3 1 dB. The intrinsic mixer noise is found to vary between 17–19 K, of which 9 K is attributed to shot noise associated with leakage current below the gap. To improve reliability, the IF circuit and bias injection are entirely planar by design. The instrument was successfully installed at the Caltech Submillimeter Observatory (CSO), Mauna Kea, HI, in October 2006

Design of a 2.4 GHz High-Performance Up-Conversion Mixer with Current Mirror Topology

In this paper, a low voltage low power up-conversion mixer, designed in a Chartered 0.18 μm RFCMOS technology, is proposed to realize the transmitter front-end in the frequency band of 2.4 GHz. The up-conversion mixer uses the current mirror topology and current-bleeding technique in both the driver and switching stages with a simple degeneration resistor. The proposed mixer converts an input of 100 MHz intermediate frequency (IF) signal to an output of 2.4 GHz radio frequency (RF) signal, with a local oscillator (LO) power of 2 dBm at 2.3 GHz. A comparison with conventional CMOS up-conversion mixer shows that this mixer has advantages of low voltage, low power consumption and high-performance. The post-layout simulation results demonstrate that at 2.4 GHz, the circuit has a conversion gain of 7.1 dB, an input-referred third-order intercept point (IIP3) of 7.3 dBm and a noise figure of 11.9 dB, while drawing only 3.8 mA for the mixer core under a supply voltage of 1.2 V. The chip area including testing pads is only 0.62×0.65 mm2