Design of a novel low-power 4th-order 1.7 GHz CMOS frequency synthesizer for DCS-1800

A low-power fully-integrated type-2 4th-order 1.7 GHz CMOS frequency synthesizer for DCS-1800 application is designed and simulated in a 0.25 μm process technology. The frequency switching is achieved using a novel architecture exploiting a direct digital synthesis (DDS) device as the frequency reference. The new topology significantly lowers the undesired sideband power due to divider ratio switching by directly shifting the frequency of the DDS reference. The frequency synthesizer (excluding the DDS device) dissipates only 9 mW of power from a 2 V power supply. It employs a fast-switching novel charge pump circuit and a low-noise fully-integrated differential LC voltage controlled oscillator using on-chip spiral inductors and accumulation-mode capacitors to meet the requirements of a DCS-1800 system. A detailed analysis of the phase noise in the 4th order loop is presented

Design and distortion analysis of fully integrated image reject RF CMOS frontends

This thesis presents the design and experimental results of a 7.3GHz notch image reject filter, combined with a 5.8GHz low-noise amplifier (LNA), for integrated heterodyne receiver front-ends. A new image reject filter implementation is proposed. Q-enhancement circuitry for on-chip inductors are used to optimize the depth of image rejection. Experimental results show that more than 62dB of image rejection at 7.3GHz can be obtained in a standard CMOS 0.18mum technology, while operating from a 1.8V supply. The LNA exhibits a gain of 15.8dB and an IIP3 of -5.3dBm while consuming 9mW of power. With maximum image rejection, the LNA-notch combination circuit achieves a 4.1dB noise figure at 5.8GHz. The proposed notch filter alone can operate from a 1V supply voltage. It is shown analytically how circuit stability can be ensured.The implementation of new robust and stable high-Q CMOS image reject filters, which enables the realization of fully integrated heterodyne 5GHz RF receivers is also presented. A cascade of two notch filters with their image reject frequencies slightly offsetted is proposed, in order to obtain a wide image rejection bandwidth, without having to resort to the overhead of automatic tuning circuitry. Thus, power consumption, area, and complexity are significantly reduced. Experimental results show that more than 30d$ of image rejection can be obtained in a standard 0.18mum CMOS technology, over a 400MHz bandwidth centered at 7.4GHz

Design of frequency synthesizers for short range wireless transceivers

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts