Design of a 10GHz RF power amplifier in 130nm CMOS technology based on Wilkinson combiner methodology

There is a growing demand today to design and fabricate RF power amplifiers at high frequencies above 5GHz that can directly drive a 50Ω antenna with sufficiently high transmission power to meet the needs of various wireless communication applications. This has typically been done by using GaN or other III-V technologies to build the power amplifier transistor, in order to allow for the use of much higher power supply voltages, than are used in today’s silicon technologies. For example, a 5W GaN power amplifier at 5GHz would typically make use of a VDD of 5V to 10V, and would be done as a discrete device on a separate module from the RF analog circuitry built out of silicon. With the continuing evolution of Moore’s Law, silicon technologies in use today for high frequency wireless communications typically are using VDD of 1.5V or less. There is a desire, however, in many wireless applications to be able to place the RF power amplifier on the same silicon chip as all the other RF/analog IC circuitry, in order to save chip fabrication cost. Consequently, research in improved methods of RF power amplifier design in silicon technology is being done in many IC design laboratories in order to increase the RF power output of power amplifiers built in silicon. This MS Thesis proposes the complete design of a four channel RF power amplifier by using the Wilkinson combiner with 27dBm output power. All the circuits are designed and implemented based on the Global Foundries 130nm SiGe BiCMOS technology and design kit at a frequency of 10GHz with a VDD = 1.5V, to provide 0.5W of RF output signal power into a 50Ω antenna

Design of stacked-MOS transistor mm-wave class C amplifiers for Doherty power amplifiers

Abstract This paper discusses the design requirements of class C auxiliary (aux) amplifiers deployed in Doherty power amplifiers (DPA). Taking conduction angle and back-off (BO) level into account a global design chart is presented which can be utilized to properly dimension the aux amplifier. Based on the proposed method a class C power amplifier is designed and exploited in a DPA circuit at 28GHz which is evaluated using simulations based on 45nm CMOS technology. Simulations reveal 27dBm saturated output power, 60% maximum drain efficiency (DE), 45% DE at 6dB BO, and 2 times efficiency enhancement at 6dB BO which is a new record in this trend