Design of Robust CMOS Amplifiers Combining Advanced Low-Voltage and Feedback Techniques

Part 15: ElectronicsInternational audienceThis paper describes and tries to demystify the use of different low-voltage operation devices, such as dynamic threshold MOS transistors (DTMOS) with feedback techniques such as regulated-feedforward (RFF) and self-biasing (SB). Traditionally, DTMOS devices are only used when nominal supply voltages below 0.7 V are envisaged. Moreover, RFF and SB techniques are normally avoided since engineers designing high-performance amplifiers are afraid of additional stability concerns. This work demonstrates, through exhaustive simulation results over process, temperature and supply (PVT) corners using a standard 130 nm 1.2 V CMOS technology that, employing DTMOS in some specific devices can improve some performance parameters such as the open-loop low-frequency gain and, simultaneously, reduce significantly the variability over PVT corners. Moreover, it is also demonstrated that, there is no risk of operating at supply voltages higher than 1.2 V. Combining DTMOS with RFF and SB allows achieving reasonable gain-bandwidth products (GBW) even operating at low-voltage (down to 0.7 V), together averaged power savings of the order of 8% and highly simplifies the design of the circuit (since no biasing circuitry is required)

Design of a low-voltage CMOS RF receiver for energy harvesting sensor node

In this thesis a CMOS low-power and low-voltage RF receiver front-end is presented. The main objective is to design this RF receiver so that it can be powered by a piezoelectric energy harvesting power source, included in a Wireless Sensor Node application. For this type of applications the major requirements are: the low-power and low-voltage operation, the reduced area and cost and the simplicity of the architecture. The system key blocks are the LNA and the mixer, which are studied and optimized with greater detail, achieving a good linearity, a wideband operation and a reduced introduction of noise. A wideband balun LNA with noise and distortion cancelling is designed to work at a 0.6 V supply voltage, in conjunction with a double-balanced passive mixer and subsequent TIA block. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver analog front-end has a total voltage conversion gain of 31.5 dB, a 0.1 - 4.3 GHz bandwidth, an IIP3 value of -1.35 dBm, and a noise figure lower than 9 dB. The total power consumption is 1.9 mW and the die area is 305x134.5 m2, using a standard 130 nm CMOS technology