Baseband-processor for a passive UHF RFID transponder

This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID transponders, and proposes different techniques for reducing its power consumption. The processor has been implemented in a 0.35μm CMOS technology process using automatic tools for both the logic synthesis and layout. Post-layout simulations confirm the fully functionality of the prototype and predict a worst-case power consumption of only 2.9μA at 1.2V supply.Ministerio de Educación y Ciencia TEC2006-03022, TEC2009-08447Junta de Andalucía TIC-0281

Baseband Processor Design of Multi-purpose RFID Tag

Radio frequency identification has found ubiquitous usage in today‟s industry. Object identification and tracking, supply chain management, anti-theft and fraud systems are just some of the uses RFID tags find in today‟s market. As the RFID technology competes with other technologies present in the market, a large amount of research has been undertaken in order to optimize the performance and cost factors of the readers and tags involved in the RFID system. Various implementations on different devices such as ICs and CMOS System on Chip (Soc) have been tried out. FPGAs are also being considered as a potential target device for implementing RFID systems. This project aims at the design of an FPGA implementable RFID Tag processor design for the purpose of baseband signal processing. A new architecture has been proposed and implemented for this processor. This architecture takes into consideration the flexibility of the entire system with the help if independent sub modules. Also, the suggested architecture has taken into consideration the creation of an innovative single tag for multiple purposes which can interact with various types of readers and convey the required information to each one of them. The RFID tag has been designed in accordance to EPCglobal Class1 Generation2 standard for operation in the range of 860-960 MHz in the air interface. The design of the tag components has been done with the help of XILINX and the verifications and analysis with ModelSim

Work in Progress: RFID Sports Timing System

Timing plays a critical role in most sporting events. RFID-based timing solutions offer a high level of automation. Current timing solutions are high in cost and frequently do not offer live results to spectators. Existing RFID hardware is evaluated for suitability in a new timing solution. An architecture for an open source timing solution is then evaluated. The new solution offers a novel combination of features making ownership feasible for smaller sporting events

Radio Frequency Identification: The Current and Future Solutions for Privacy and Security

Thesis written by a student in the UNT Honors College discussing the standards, protocols, "attack models," and security algorithms of Radio Frequency Identification technology

Modelagem de sistemas heterogêneos utilizando frameworks baseados em MoC

Monografia (graduação)—Universidade de Brasília, Faculdade UnB Gama, Curso de Engenharia Eletrônica, 2014.O presente texto apresenta uma proposta de trabalho de conclusão de curso que consiste na modelagem em alto nível e na simulação de sistemas heterogêneos utilizando um ambiente baseado na teoria de modelos de computação (MoC). O objetivo principal do trabalho é modelar uma tag de RFID como estudo de caso usando a linguagem SystemC e sua extensão SystemC-AMS. Com isso, será possível verificar a funcionalidade da arquitetura proposta através de simulações em alto nível de abstração, bem como disponibilizar protótipos virtuais do sistema, incluindo a funcionalidade das partes analógicas/RF e digital da tag. Neste documento são apresentados os conceitos teóricos necessários para o desenvolvimento do trabalho, a modelagem efetuada e os resultados da simulação da tag de RFID utilizado como estudo de caso.In this text, we present a proposal for an undergraduate project, which consists on the high level modeling and simulation of heterogeneous systems using one framework based on models of computation (MoC) theory. The main goal of this work is to model an tag of RFID system as a case study using SystemC language, its extension SystemC-AMS. With these models, it will be possible to verify the functionality of the proposed architecture using simulations in a high abstraction level. In addition, a virtual prototype of the system, including the analog/RF and digital blocks of tag, will be available. In this document, we summarize the basic concepts needed to describe the models and present the modeling and results of the tag of the RFID system used as a case study

Adiabatic Approach for Low-Power Passive Near Field Communication Systems

This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen. Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed. Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock. Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches