Matrix multiplication using quantum-dot cellular automata to implement conventional microelectronics

Quantum-dot cellular automata (QCA) shows promise as a post silicon CMOS, low power computational technology. Nevertheless, to generalize QCA for next-generation digital devices, the ability to implement conventional programmable circuits based on NOR, AND, and OR gates is necessary. To this end, we devise a new QCA structure, the QCA matrix multiplier (MM), employing the standard Coulomb blocked, five quantum dot (QD) QCA cell and quasi-adiabatic switching for sequential data latching in the QCA cells. Our structure can multiply two N x M matrices, using one input and one bidirectional input/output data line. The calculation is highly parallelizable, and it is possible to achieve reduced calculation time in exchange for increasing numbers of parallel matrix multiplier units. We show convergent, ab initio simulation results using the Intercellular Hartree Approximation for one, three, and nine matrix multiplier units. The structure can generally implement any programmable logic array (PLA) or any matrix multiplication based operation.Comment: 14 pages, 9 figures, supplemental informatio

Implementation of multi-CLB designs using quantum-dot cellular automata

CMOS scaling is currently facing a technological barrier. Novel technologies are being proposed to keep up with the need for computation power and speed. One of the proposed ideas is the quantum-dot cellular automata (QCA) technology. QCA uses quantum mechanical effects in the device at the molecular scale. QCA systems have the potential for low power, high density, and regularity. This thesis studies QCA devices and uses those devices to build a simple field programmable gate array (FPGA). The FPGA is a combination of multiple configure logical blocks (CLBs) tiled together. Most previous work on this area has focused on fixed logic and programmable interconnect. In contrast, the work at the Rochester Institute of Technology (RIT) has designed and simulated a configurable logic block (CLB) based on look-up tables (LUTs). This thesis presents a simple FPGA that consists of multiple copies of the CLB created by the RIT group. The FPGA is configured to emulate a ripple-carry adder and a bit-serial multiplier. The latency and throughput of both functions are analyzed. We employ a multilevel approach to design specification and simulation. QCADesigner software is used for layout and simulation of an individual CLB. For the FPGA, the high-level HDLQ Verilog library is used. This hybrid approach provides a high degree of confidence in reasonable simulation time

Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

Interleaving in Systolic-Arrays: a Throughput Breakthrough

In past years the most common way to improve computers performance was to increase the clock frequency. In recent years this approach suffered the limits of technology scaling, therefore computers architectures are shifting toward the direction of parallel computing to further improve circuits performance. Not only GPU based architectures are spreading in consideration, but also Systolic Arrays are particularly suited for certain classes of algorithms. An important point in favor of Systolic Arrays is that, due to the regularity of their circuit layout, they are appealing when applied to many emerging and very promising technologies, like Quantum-dot Cellular Automata and nanoarrays based on Silicon NanoWire or on Carbon nanotube Field Effect Transistors. In this work we present a systematic method to improve Systolic Arrays performance exploiting Pipelining and Input Data Interleaving. We tackle the problem from a theoretical point of view first, and then we apply it to both CMOS technology and emerging technologies. On CMOS we demonstrate that it is possible to vastly improve the overall throughput of the circuit. By applying this technique to emerging technologies we show that it is possible to overcome some of their limitations greatly improving the throughput, making a considerable step forward toward the post-CMOS era

Designing a Novel Reversible Systolic Array Using QCA

Many efforts have been done about designing nano-based devices till today. One of these devices is Quantum Cellular Automata (QCA). Because of astonishing growth in VLSI circuits Designs in larger scales and necessity of feature size reduction, there is more need to design complicated control systems using nano-based devices. Besides, since there is a critical manner of temperature in QCA devices, complicated systems using these devices should be designed reversibly. This article has been proposed a novel architecture for QCA circuits in order to utilizing in complicated control systems based on systolic arrays with high throughput and least power dissipation