ADC Emulation on FPGA

Analog-to-Digital Converters (ADCs) are devices that transform analog signals into digital signals and are used in various applications such as audio recording, data acquisition, and measurement systems [1]. Prior to the development of actual chip, there is a need for prototyping, testing and verifying the performance of ADCs in different scenarios. Analog macros cannot be tested on an FPGA. In order to ensure the macros function properly, the emulation of the ADC is done first. This is a digital module and can be designed in System Verilog. This paper demonstrates the design of the module on FPGA for Analog to Digital Converter (ADC) emulation. The emulation is done specific to the ADC macro which has programmable resolutions of 12, 10, 8 or 6 bits. To validate the simulation results, the designed module is tested on FPGA. The outputs and logic block utilization are analyzed. The number of LUTs utilized in the design is 38, the number of flip flops needed is 41 and the input output pin utilization is 20. The dynamic power utilization of the design is 0.543W and the static power utilization is 0.082W

ADC Emulation on FPGA

Analog-to-Digital Converters (ADCs) are devices that transform analog signals into digital signals and are used in various applications such as audio recording, data acquisition, and measurement systems [1]. Prior to the development of actual chip, there is a need for prototyping, testing and verifying the performance of ADCs in different scenarios. Analog macros cannot be tested on an FPGA. In order to ensure the macros function properly, the emulation of the ADC is done first. This is a digital module and can be designed in System Verilog. This paper demonstrates the design of the module on FPGA for Analog to Digital Converter (ADC) emulation. The emulation is done specific to the ADC macro which has programmable resolutions of 12, 10, 8 or 6 bits. To validate the simulation results, the designed module is tested on FPGA. The outputs and logic block utilization are analyzed. The number of LUTs utilized in the design is 38, the number of flip flops needed is 41 and the input output pin utilization is 20. The dynamic power utilization of the design is 0.543W and the static power utilization is 0.082W