Space Shuttle: A test vehicle for the reliability of the SkyWater 130nm PDK for future space processors

Recently the ASIC industry experiences a massive change with more and more small and medium businesses entering the custom ASIC development. This trend is fueled by the recent open hardware movement and relevant government and privately funded initiatives. These new developments can open new opportunities in the space sector – which is traditionally characterised by very low volumes and very high non-recurrent (NRE) costs – if we can show that the produced chips have favourable radiation properties. In this paper, we describe the design and tape-out of Space Shuttle, the first test chip for the evaluation of the suitability of the SkyWater 130nm PDK and the OpenLane EDA toolchain using the Google/E-fabless shuttle run for future space processors.This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments”. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033) and the European Community’s Horizon Europe programme under the METASAT project (grant agreement 101082622).Peer ReviewedPostprint (author's final draft

Design for mitigation of single event effects

ISBN: 0769524060Various fault tolerant techniques can be employed to mitigate SEUs, SETs and SELs. However, such techniques usually inquire high hardware, speed and power penalty that most commercial applications could not afford. This presentation concerns low cost mitigation techniques for single-event effects induced by alpha particles and atmospheric neutrons in advanced nanometric designs