The high speed buffer board : a SAIL EIA-485 communications accelerator card for the vector measuring current meter

A High Speed Buffer Board (HSBB) has been developed for the Vector Measuring Current Meter (VMCM) to implement the transmission of data at 9600 baud over an EIA-485 link. The HSBB significantly extends the VMCM communication functionality, which was previously limited to 300 baud transmission via 20 mA current loop or FSK telemetry. The increased speed allows rapid sampling of a large number of current meters on a common cable and the EIA-485 circuitry, which was designed for low power operation, provides a useful multipoint communication method for data transmission over long cable lengths. SAIL protocol (IEEE 997) was utilized to coordinate data transfer by the instruments on a common link. An MC68HC11 microcontroller resides in the VMCM, buffering data it receives at 300 baud from the VMCM UART. In response to a jumper selectable SAIL address, the MC68HC11 offloads the data at 9600 baud via EIA-485 to the SAIL controller. Synchronous data collection from many instruments is ensured by the SAIL synoptic set command and an embedded resynchronization/reset command. The low power consumption allows deployments of six months or more with a standard VMCM battery stack.Funding was provided by the Office of Naval Research under Contract No. N00014-84-C-0134 and Grant No. N00014-90-J-1495

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording

Feasibility of self-structured current accessed bubble devices in spacecraft recording systems

The self-structured, current aperture approach to magnetic bubble memory is described. Key results include: (1) demonstration that self-structured bubbles (a lattice of strongly interacting bubbles) will slip by one another in a storage loop at spacings of 2.5 bubble diameters, (2) the ability of self-structured bubbles to move past international fabrication defects (missing apertures) in the propagation conductors (defeat tolerance), and (3) moving bubbles at mobility limited speeds. Milled barriers in the epitaxial garnet are discussed for containment of the bubble lattice. Experimental work on input/output tracks, storage loops, gates, generators, and magneto-resistive detectors for a prototype device are discussed. Potential final device architectures are described with modeling of power consumption, data rates, and access times. Appendices compare the self-structured bubble memory from the device and system perspectives with other non-volatile memory technologies

RFID LOGIN SYSTEM For COMPUTERS

This report covers the implementation of RFID Login System for computers. The objective of this project is to replace the existing smart card used to login to a computer, with RFID technology. RFID technology is identified as the best alternative for smart card, due to its high level of security. The project scope is to fabricate RFID tag and reader for computer login. The transponder will transmit the signal containing user's information upon activation and the reader will process the information for verification purposes. The scope of the study is mainly about the architecture of RFID and how to develop hardware related to RFID. A prototype mainly consists of microcontroller application, radio frequency data transmission circuitry and graphical user interface was successfully developed. The prototype can be effectively used for computer login, based on RFID technology.

YUSOF @GHANI

PIC16 small prototyping board is the microcontroller development board that holding a microcontroller and other required circuitry used for application or embedded system development. The board is directly useful to an application developer, without require spending time and effort in developing the controller board. The purpose of this project is to develop a working prototype, PIC16 small prototyping board that used for rapid prototyping. The board is based on PIC16F628A microcontroller. The board design is similar to Arduino Uno board. ExpressPCB and ExpressSCH are used to design the board before it is fabricated. After that, the prototype is fabricated and the testing is carried out to observe the performance of the device. The switches and LEDs are placed on the board to test each input output of the board. The result of the tested board is summarized in the end of this project

STR: a student developed star tracker for the ESA-LED ESMO moon mission

In the frame of their engineering degree, ISAE’s students are developing a Star Tracker, with the aim of being the core attitude estimation equipment of the European Moon Student Orbiter. This development goes on since several years and is currently in phase B. We intend to start building an integrated breadboard for the end of the academic year. The STR is composed of several sub-systems: the optical and detection sub-system, the electronics, the mechanics and the software. The optical detection part is based on an in-house developed new generation of APS detectors. The optical train is made of several lenses enclosed in a titanium tube. The electronics includes a FPGA for the pre-processing of the image and a microcontroller in order to manage the high level functions of the instrument. The mechanical part includes the electronics box, as well as the sensor baffle. The design is optimized to minimize the thermo-elastic noise of the assembly. Embedded on ESMO platform, this Star Tracker will be able to compute the satellite‘s attitude, taking into account the specific requirements linked to a Moon mission (illumination, radiation requirements and baffle adaptation to lunar orbit). In order to validate the design, software end-to-end simulation will include a complete simulation of the STR in its lunar dynamic environment. Therefore, we are developing a simple orbital model for the mission (including potential dazzling by celestial bodies)