2 research outputs found
λΉμ© ν¨μ¨μ μΈ ν΄λ λ° νμ κ²μ΄ν μ€κ³ λ°©λ²λ‘
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Όλ¬Έ(λ°μ¬)--μμΈλνκ΅ λνμ :곡과λν μ κΈ°Β·μ 보곡νλΆ,2020. 2. κΉνν.μ μ λ ₯ μ€κ³λ μ΅μ μμ€ν
-μ¨-μΉ© (SoCs) μ€κ³μμ λ§€μ° μ€μν μμ μ€μ νλμ΄λ€. λ³Έ λ
Όλ¬Έμμλ λμ λ° μ μ μ λ ₯ μλΉλ₯Ό κ°μμν€κΈ° μν μ μ λ ₯ μ€κ³ λ°©λ²λ‘ μ λν΄ λ
Όνλ€. ꡬ체μ μΌλ‘ λΉμ© ν¨μ¨μ μΈ μ μ λ ₯ μ€κ³λ₯Ό μνμ¬ λ κ°μ§ μλ‘μ΄ κΈ°μ μ μ μνλ€.
μ°μ λ³Έ λ
Όλ¬Έμμλ λμ μ λ ₯ μλΉλ₯Ό μ€μΌ μ μλ μλ‘μ΄ ν΄λ κ²μ΄ν
λ°©λ²μ μ μνλ€. κΈ°μ‘΄ ν립-νλ μ
λ ₯ λ°μ΄ν° ν κΈ κΈ°λ° ν΄λ κ²μ΄ν
μ κ°μ₯ λ리 μ¬μ©λλ ν΄λ κ²μ΄ν
κΈ°λ² μ€μ νλμ΄λ€. νμ§λ§ μ΄ λ°©λ²μ λ λ§μ ν립-νλμ λν΄ μ μ©ν μλ‘ ν΄λ κ²μ΄ν
μ νμν λΆκ° νλ‘κ° κΈκ²©ν μ¦κ°νλ€λ κ·Όλ³Έμ μΈ νκ³λ₯Ό μ§λκ³ μλ€. μ΄λ¬ν νκ³λ₯Ό 극볡νκΈ° μνμ¬ λ³Έ λ
Όλ¬Έμμλ λ€μκ³Ό κ°μ΄ μλ‘μ΄ ν΄λ κ²μ΄ν
λ°©λ²μ μ μνλ€. 첫 λ²μ§Έλ‘ κΈ°μ‘΄ μ
λ ₯ λ°μ΄ν° ν κΈ κΈ°λ° ν΄λ κ²μ΄ν
λ°©λ²μ νμν νλ‘ μμμ λΆμνμ¬ ν΄λΉ λ°©λ²μ λΉν¨μ¨μ±μ 보μ΄κ³ , κΈ°μ‘΄ λ°©λ²μμ μ¬μ©λλ μ
λ ₯ λ°μ΄ν° ν κΈ κ²μΆμ νμμ μ΄μ§λ§ κ³ λΉμ©μ XOR κ²μ΄νΈλ₯Ό μλ²½ν μ κ±°ν ν립-νλ μν κΈ°λ° ν΄λ κ²μ΄ν
'μ΄λΌλ μλ‘μ΄ ν΄λ κ²μ΄ν
λ°©λ²μ μ μνλ€. λ λ²μ§Έλ‘ μ μλ XOR κ²μ΄νΈκ° νμ μλ ν΄λ κ²μ΄ν
λ°©λ²μ μν λΆκ° νλ‘λ₯Ό μ μνλ©°, λ€μν νμ΄λ° λΆμμ ν΅νμ¬ ν΄λΉ νλ‘κ° μμ μ μΌλ‘ μ μ©λ μ μμμ 보μΈλ€. μΈ λ²μ§Έλ‘ νλ‘μ ν립-νλ μν νλ‘νμΌμ κΈ°λ°νμ¬, μ μλ ν΄λ κ²μ΄ν
κΈ°λ²μ κΈ°μ‘΄ ν΄λ κ²μ΄ν
κΈ°λ²κ³Ό μλ²½νκ² ν΅ν©ν μ μλ ν΄λ κ²μ΄ν
λ°©λ²λ‘ μ μ μνλ€. μ¬λ¬ λ²€μΉλ§ν¬ νλ‘μ λν μ€ν κ²°κ³Όλ κΈ°μ‘΄ μ
λ ₯ λ°μ΄ν° ν κΈ κΈ°λ° ν΄λ κ²μ΄ν
λ°©λ²μ΄ μ λ ₯ μλΉ μ κ° κΈ°νλ₯Ό λμΉλ λ°λ©΄ λ³Έ λ
Όλ¬Έμμ μ μλ λ°©λ²μ λͺ¨λ νμ΄λ° μ μ½ μ‘°κ±΄μ λ§μ‘±νλ©΄μ μ λ ₯ μλΉ κ°μμ λ§€μ° ν¨κ³Όμ μμ 보μ¬μ€λ€.
λ€μμΌλ‘ μ μ μ λ ₯ μλΉλ₯Ό μ€μ΄κΈ° μν λ°©μμΌλ‘, λ³Έ λ
Όλ¬Έμμλ κΈ°μ‘΄ νμ κ²μ΄νΈ νλ‘μ μν λ³΄μ‘΄μ© μ μ₯ κ³΅κ° ν λΉ λ°©λ²λ€μ΄ μ§λκ³ μλ λ κ°μ§ μ€μν νκ³λ€μ ν΄κ²°ν μ μλ λ°©λ²μ μ μνλ€. μ€μν νκ³λ€μ΄λ 첫 λ²μ§Έλ‘ λ€μ€-λΉνΈ μν 보쑴 ν립-νλμ 무λΆλ³ν μ¬μ©μΌλ‘ μΈν κΈ΄ μ¨μ΄ν¬μ
μ§μ° μκ°μ΄λ©°, λ λ²μ§Έλ‘ λ©ν°νλ μ λλ¨Ήμ 루νκ° μλ μν 보쑴 ν립-νλμ μ΅μ ν λΆκ°λ₯μ±μ΄λ€. κΈ°μ‘΄ λ°©λ²λ€μμλ μν 보쑴μ μν μ μ₯ 곡κ°μ μ΅μννκΈ° μν΄ κΈ΄ μ¨μ΄ν¬μ
μ§μ° μκ°μ΄ νμμ μ΄μλ€. κ·Έλ¦¬κ³ λλ¨Ήμ 루νκ° μλ ν립-νλμ μ΅μ νν μ μλ λμμΌλ‘ λ€λ£¨μ΄μ‘λ€. κ·Έλ¬λ μΌλ°μ μΌλ‘ νλμ¨μ΄ κΈ°μ μΈμ΄(HDL)λ‘λΆν° μμ±λλ λλ¨Ήμ 루νλ₯Ό μ§λ ν립-νλμ 무μν μ μμ μ λλ‘ μ μ μμ΄ μλλ€. 첫 λ²μ§Έ νκ³λ₯Ό ν΄κ²°νκΈ° μν λ°©λ²μΌλ‘ λ³Έ λ
Όλ¬Έμμλ μ΅λ 2 λΉνΈμ λ€μ€-λΉνΈ μν 보쑴 ν립-νλμ μ¬μ©νμ¬ μ¨μ΄ν¬μ
μ§μ° μκ°μ λ ν΄λ μ¬μ΄ν΄λ‘ μ ννλ©΄μλ μν 보쑴μ μν μ μ₯ 곡κ°μ ν¨μ¨μ μΌλ‘ μ μ½ν μ μμμ 보μΈλ€. κ·Έλ¦¬κ³ λ λ²μ§Έ νκ³λ₯Ό 극볡νκΈ° μν΄μ λλ¨Ήμ 루νλ₯Ό μ§λ ν립-νλμ΄ ν¬ν¨λ λ ν립-νλ μμ μνλ₯Ό 볡μν μ μλ 2λ¨ μν 보쑴 μ μ΄ λ°©μμ μ μνλ€. λν μ£Όμ΄μ§ νλ‘μμ μΆ©λμμ΄ λμμ μ‘΄μ¬ν μ μλ ν립-νλ μμ μ΅λλ‘ μΆμΆνκΈ° μν΄ λ
립 μ§ν© λ¬Έμ (independent set problem)κΈ°λ°μ μ°μ°λ²λ μ μνλ€. λ²€μΉλ§ν¬ νλ‘μ λν μ€ν κ²°κ³Όλ λ³Έ λ
Όλ¬Έμμ μ μλ λ°©λ²μ΄ μ¨μ΄ν¬μ
μ§μ° μκ°μ λ ν΄λ μ¬μ΄ν΄λ‘ μ ννλ©΄μλ μν 보쑴μ νμν μ μ₯ 곡κ°κ³Ό νμλ₯Ό κ°μμν€λλ° λ§€μ° ν¨κ³Όμ μμ 보μ¬μ€λ€.Low power design is of great importance in modern system-on-chips (SoCs). This dissertation studies on low power design methodologies for saving dynamic and static power consumption. Precisely, we unveil two novel techniques of cost effective low power design.
Firstly, we propose a novel clock gating method for reducing the dynamic power consumption. Flip-flop's input data toggling based clock gating is one of the most commonly used clock gating methods, in which one critical and inherent limitation is the sharp increase of gating logic as more flip-flops are involved in gating. In this dissertation, we propose a new clock gating method to overcome this limitation. Specifically, (1) we analyze the resources of gating logic in the input data toggling based clock gating, from which an ineffectiveness in resource utilization is observed and we propose a new clock gating technique called flip-flop state driven clock gating which completely eliminates the essential and expensive component of XOR gates for detecting input toggling of flip-flops; (2) we provide the supporting logic circuitry of our proposed XOR-free clock gating, confirming its safe applicability through a comprehensive timing analysis; (3) we propose, based on the flip-flops' state profile, a clock gating methodology that seamlessly combines our flip-flop state based clock gating with the toggling based clock gating. Through experiments with benchmark circuits, it is confirmed that our clock gating method is very effective in reducing power, which otherwise the toggling based clock gating shall miss the power saving opportunity, while meeting all timing constraints.
Secondly, for reducing the static power consumption, we solve two critical limitations of the conventional approaches to the allocation of state retention storage for power gated circuits. Those are (1) the long wakeup delay caused by the senseless use of multi-bit retention flip-flops (MBRFFs) and (2) the inability to optimize retention flip-flops for the flip-flops with mux-feedback loop. It should be noted that the conventional approaches have regarded the long wakeup delay as an inevitable consequence of maximizing the reduction of total storage size for state retention while they have treated the flip-flops with mux-feedback loop (called self-loop flip-flop) as nonoptimizable component, but practically, the self-loop flip-flops synthesized from hardware description language (HDL) code are not far from a small amount and thus, can in no way be negligible. More precisely, for solving (1), we show that the use of MBRFFs with up to two bits, consequently, constraining the wakeup delay to no more than two clock cycles, is enough to maintain the high reduction of total retention storage and for solving (2), we devise a 2-phase retention control mechanism for a pair of flip-flops, one of which has self-loop, by which just a single retention bit can be used to restore state of the two flip-flops, and propose an independent set based algorithm for maximally extracting the non-conflict pairs from circuits. Through experiments with benchmark circuits, it is shown that our proposed method is very effective against reducing the state retention storage and the power consumption compared with the existing best MBRFF allocation while the wakeup delay is strictly limited to two clock cycles.1 INTRODUCTION 1
1.1 Clock Gating 1
1.2 Power Gating and State Retention 3
1.3 Multi-bit Retention Registers 4
1.4 Contributions of This Dissertation 6
2 FLIP-FLOP STATE DRIVEN CLOCK GATING: CONCEPT, DESIGN, AND METHODOLOGY 9
2.1 Motivations 9
2.1.1 Toggling based Clock Gating 9
2.1.2 Area and Power by Clock Gating 10
2.2 The Proposed Clock Gating 13
2.2.1 Concept of Flip-flop State Driven Clock Gating 13
2.2.2 Design of Gating Logic Circuitry 17
2.2.3 Integrated Clock Gating Methodology 22
2.2.4 Cost Formulation 23
2.3 Experiments 25
2.3.1 Experimental Setup 25
2.3.2 Experimental Results 26
3 ALGORITHM AND DESIGN OPTIMIZATION OF ALLOCATING MULTI-BIT RETENTION FLIP-FLOPS FOR POWER GATED CIRCUITS 32
3.1 Motivations 32
3.1.1 Flip-flops with Mux-feedback Loop 32
3.1.2 Impact of Wakeup Delay 37
3.2 The Proposed Allocation Algorithm 39
3.3 Design of Multi-Bit Retention Flip-Flop and Multi-Bit Extension 48
3.3.1 Multi-Bit Retention Flip-Flop 48
3.3.2 Multi-Bit Flip-Flop Extension 52
3.4 Experiments 54
3.4.1 Experimental Setup 54
3.4.2 Experimental Results 57
4 CONCLUSIONS 65
4.1 Flip-flop State Driven Clock Gating: Concept, Design, and Methodology 65
4.2 Algorithm and Design Optimization of Allocating Multi-bit Retention Flip-flops for Power Gated Circuits 66
Abstract (In Korean) 71Docto
Clock Tree and Flip-flop Co-optimization for Reducing Power Consumption and Power/Ground Noise of Integrated Circuits and Systems
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Όλ¬Έ (λ°μ¬)-- μμΈλνκ΅ λνμ 곡과λν μ κΈ°Β·μ»΄ν¨ν°κ³΅νλΆ, 2017. 8. κΉνν.For very-large-scale integration (VLSI) circuits, the activation of all flip-flops that are used to store data is synchronized by clock signals delivered through clock networks. Due to very high frequency of clock signal switches, the dynamic power consumed on clock networks takes a considerable portion of the total power consumption of the circuits. In addition, the largest amount of power consumption in the clock networks comes from the flip-flops and the buffers that drive the flip-flops at the clock network boundary. In addition, the requirement
of simultaneously activating all flip-flops for synchronous circuits induces a high peak power/ground noise (i.e., voltage drop) at the clock boundary.
In this regards, this thesis addresses two new problems: the problem of reducing the clock power consumption at the clock network boundary, and the problem of reducing the peak current at the clock network boundary. Unlike the prior works which have considered the optimization of flip-flops and clock buffers separately, our approach takes into account the co-optimization of flip-flops and clock buffers. Precisely, we propose four different types of hardware component that can implement a set of flip-flops and their driving buffer as a single unit.
The key idea for the derivation of the four types of clock boundary component is that one of the inverters in the driving buffer and one of the inverters in each flip-flop can be combined and removed without changing the functionality of the flip-flops. Consequently, we have a more freedom to select (i.e., allocate) clock boundary components that is able to reduce the power consumption or peak current under timing constraint. We have implemented our approach of clock boundary optimization under bounded clock skew constraint and tested it with ISCAS 89 benchmark circuits. The experimental results confirm that our approach is able to reduce the clock power consumption by 7.9βΌ10.2% and power/ground noise by 27.7%βΌ30.9% on average.Chapter 1 Introduction 1
1.1 Clock Signal 1
1.2 Metrics of Clock Design 2
1.3 Clock Network Topologies 4
1.4 Multibit Flip-flop 5
1.5 Simultaneous Switching Noise 6
1.6 Contributions of This Dissertation 6
Chapter 2 Clock Tree and Flip-flop Co-optimization for Reducing Power Consumption 8
2.1 Introduction 8
2.2 Types of Boundary Optimization 9
2.3 Analysis of Four Types of Flip-flop 12
2.3.1 Internal Power Comparison 12
2.3.2 Characterization of Power Consumption 14
2.4 Problem Formulation 15
2.5 The Proposed Algorithm 17
2.5.1 Independence Assumption 17
2.5.2 BoundaryMin Algorithm 17
2.6 Experimental Results 29
2.6.1 Experimental Setup 29
2.6.2 Clock Tree Boundary Optimization Results 33
2.6.3 Capacitance Analysis on Flip-flops 38
2.6.4 Slew and Skew Analysis 39
2.6.5 Window Width Analysis 39
2.7 Conclusions 41
Chapter 3 Clock Tree and Flip-flop Co-optimization for Reducing Power/Ground Noise 42
3.1 Introduction 42
3.2 Current Characteristic of Four Types of Flip-flop 45
3.3 Motivational Example 47
3.4 Problem Formulation 52
3.5 Proposed Algorithm 54
3.5.1 An Overview 54
3.5.2 Superposition of Current Flows 55
3.5.3 Formulation to Instance of MOSP Problem 57
3.5.4 Selecting Target Power Grid Points 59
3.5.5 Consideration of Reducing Power Consumption 62
3.6 Experimental Results 62
3.7 Summary 65
Chapter 4 Conclusion 68
4.1 Clock Buffer and Flip-flop Co-optimization for Reducing Power Consumption 68
4.2 Clock Buffer and Flip-flop Co-optimization for Reducing Power/Ground Noise 69
μ΄λ‘ 78Docto