A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks

Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, Look-Up- Table-Log-BCJR (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental Add Compare Select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of- the-art Maximum Logarithmic Bahl-Cocke-Jelinek-Raviv (Max- Log-BCJR) implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m

State Space Parallelization Method for a 16-Bit Turbo Encoder

Turbo codes are widely used in digital communication systems. Their ability to reach the Shannon channel capacity made it the choice for most of the communication systems. Due to the huge amount of the transmitted data, there is a need to increase the processing speed of the encoders. The researchers used the state space technique to enhance the throughput of the turbo encoder. They apply it to increase the turbo encoder throughput from one bit per cycle up to 8 bit per cycle. The researchers applied the state space method to a three-flip flop, eight state Recursive Systematic Convolution Code circuit to achieve their goal. In this paper, we explored the state space technique and applied it to a four flip-flop Recursive Systematic Convolution Code circuit so that we can achieve a throughput of 16 bit per cycle. The circuit was designed and tested using MATLAB then implemented using FPGA to verify its operation

Communications in the observation limited regime

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 141-145).We consider the design of communications systems when the principal cost is observing the channel, as opposed to transmit energy per bit or spectral efficiency. This is motivated by energy constrained communications devices where sampling the signal, rather than transmitting or processing it, dominates energy consumption. We show that sequentially observing samples with the maximum a posteriori entropy can reduce observation costs by close to an order of magnitude using a (24,12) Golay code. This is the highest performance reported over the binary input AWGN channel, with or without feedback, for this blocklength. Sampling signal energy, rather than amplitude, lowers circuit complexity and power dissipation significantly, but makes synchronization harder. We show that while the distance function of this non-linear coding problem is intractable in general, it is Euclidean at vanishing SNRs, and root Euclidean at large SNRs. We present sequences that maximize the error exponent at low SNRs under the peak power constraint, and under all SNRs under an average power constraint. Some of our new sequences are an order of magnitude shorter than those used by the 802.15.4a standard.(cont.) In joint work with P. Mercier and D. Daly, we demonstrate the first energy sampling wireless modem capable of synchronizing to within a ns, while sampling energy at only 32 Msamples per second, and using no high speed clocks. We show that traditional, minimum distance classifiers may be highly sensitive to parameter estimation errors, and propose robust, computationally efficient alternatives. We challenge the prevailing notion that energy samplers must accurately shift phase to synchronize with high precision.by Manish Bhardwaj.Ph.D

Energy-efficient design and implementation of turbo codes for wireless sensor network

The objective of this thesis is to apply near Shannon limit Error-Correcting Codes (ECCs), particularly the turbo-like codes, to energy-constrained wireless devices, for the purpose of extending their lifetime. Conventionally, sophisticated ECCs are applied to applications, such as mobile telephone networks or satellite television networks, to facilitate long range and high throughput wireless communication. For low power applications, such as Wireless Sensor Networks (WSNs), these ECCs were considered due to their high decoder complexities. In particular, the energy efficiency of the sensor nodes in WSNs is one of the most important factors in their design. The processing energy consumption required by high complexity ECCs decoders is a significant drawback, which impacts upon the overall energy consumption of the system. However, as Integrated Circuit (IC) processing technology is scaled down, the processing energy consumed by hardware resources reduces exponentially. As a result, near Shannon limit ECCs have recently begun to be considered for use in WSNs to reduce the transmission energy consumption [1,2]. However, to ensure that the transmission energy consumption reduction granted by the employed ECC makes a positive improvement on the overall energy efficiency of the system, the processing energy consumption must still be carefully considered.The main subject of this thesis is to optimise the design of turbo codes at both an algorithmic and a hardware implementation level for WSN scenarios. The communication requirements of the target WSN applications, such as communication distance, channel throughput, network scale, transmission frequency, network topology, etc, are investigated. Those requirements are important factors for designing a channel coding system. Especially when energy resources are limited, the trade-off between the requirements placed on different parameters must be carefully considered, in order to minimise the overall energy consumption. Moreover, based on this investigation, the advantages of employing near Shannon limit ECCs in WSNs are discussed. Low complexity and energy-efficient hardware implementations of the ECC decoders are essential for the target applications