On zero-forcing equalization for short-filtered multicarrier faster-than-Nyquist signaling

Within the context of faster-than-Nyquist signaling, a low-complexity multicarrier system based on short-length filters and zero-forcing turbo equalization is introduced. Short-length filters allow a reduced-size block processing while zero-forcing equalization allows a linear reduced-complexity implementation. Furthermore, rectangular and out-of-band energy minimization pulse shaping demonstrates competitive performance results over an additive white Gaussian noise channel while keeping a lower computational cost than other multicarrier faster-than-Nyquist systems

Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier systems

Abstract in UndeterminedFaster-than-Nyquist (FTN) signaling is a method of improving bandwidth efficiency by transmitting information beyond Nyquist's orthogonality limit for interference free transmission. Previously have theoretically established that FTN can provide improved bandwidth efficiency. However, this comes at the cost of higher decoding complexity at the receiver. Our work has evaluated multicarrier FTN signaling for its implementation feasibility and complexity overhead compared to the gains in bandwidth efficiency. The work carried out in this research project includes a systems perspective evaluating performance, algorithm hardware tradeoffs and a hardware architecture leading to a silicon implementation of the decoder for FTN signaling. From the systems perspective, co-existence of FTN and OFDM based multicarrier system has been evaluated. OFDM being a part of many existing and upcoming broadband access technologies such as WLAN, LTE, DVB, this analogy is motivated. On the hardware aspect, the proposed architecture can accommodate both OFDM and FTN systems. The processing blocks in transmitter and receiver were designed for reuse and carry out different functions in the transceiver. Furthemore, the hardware could be configured to operate at varying bandwidth efficiencies (by FTN signaling) to exploit the channel conditions. The decoder implementation also considered block sizes and data rates to comply with the 3GPP standard. The decoding is carried out in as few as 8 iterations making it more practical for implementation in power constrained mobile devices. The decoder is implemented in 65nm CMOS process and occupies a total chip area of 0.8mm2