Design and implementation of a soft-decision decoder for Cortex codes

International audienceCortex codes are a family of rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient soft-decision decoder for Cortex codes. A dedicated algorithm is introduced that takes advantage of the particular structure of the code to simplify the decoding. Simulation results show that the proposed algorithm achieves an excellent trade-off between performance and complexity for short Cortex codes. A decoder architecture for the (32,16,8) Cortex code based on the (4,2,2) Hadamard code has been successfully designed and implemented on FPGA device. To our knowledge, this is the first efficient digital implementation of a soft-decision Cortex decoder

Design and implementation of a near maximum likelihood decoder for Cortex codes

International audienceThe Cortex codes form an emerging family among the rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient Maximum Likelihood (ML) decoder for Cortex codes. It first reviews a dedicated architecture that takes advantage of the particular structure of this code to simplify the decoding. Then, we propose a technique to improve the architecture by the generation of an optimal list of binary vectors. An optimal stopping criterion is also proposed. Simulation results show that the proposed architecture achieves an excellent performance/complexity trade-off for short Cortex codes. The proposed decoder architecture has been implemented on an FPGA device for the (24,12,8) Cortex code. This implementation supports an information throughput of 225 Mb/s. At a signal-tonoise ratio Eb/No=8 dB, the Bit Error Rate equals 2 × 10^−10, which is close to the performance of the Maximum Likelihood decoder

Decoding a family of dense codes using the sum-product algorithm and subthreshold PMOS

International audienceCortex codes are a family of block codes with goodminimum distance properties whose parity-check matrices are very dense. Digital implementations of Cortex decoders using standard decoding algorithms have not shown an acceptable performance. Motivated by the encoder structure, a new bipartite graph is introduced and exemplified for the Cortex construction of the extended Hamming code. The Cortex graph has longer girth and approximately 80% less cycles than the Tanner graph. A Cortex and an LDPC-like decoder were implemented for the same code using identical PMOS-based Gilbert multipliers. This makes them the first reported analog decoders using mainly PMOS transistors. The Cortex outperforms the LDPC-like decoder in Bit Error Rate and at the same time saves 44% of die surface. The results are supported using data from a test chip designed for a 0.25 um CMOS process