Low power data converters for specific applications

Due to increasing importance of portable equipment and reduction of the supply voltage due to technology scaling, recent efforts in the design of mixed-signal circuits have focused on developing new techniques to reduce the power dissipation and supply voltage. This requires research into new architectures and circuit techniques that enable both integration and programmability. Programmability allows each component to be used for different applications, reducing the total number of components, and increased integration by eliminating external components will reduce cost and power;Since data converters are used in many different applications, in this thesis new low voltage and low power data converter techniques at both the architecture and circuit design levels are investigated to minimize power dissipation and supply voltage. To demonstrate the proposed techniques, test the performance of the proposed architectures, and verify their effectiveness in terms of power savings, five prototype chips are fabricated and tested;First, a re-configurable data converter (RDC) architecture is presented that can be programmed as analog-to-digital converter (ADC), digital-to-analog converter (DAC), or both. The reconfigurability of the RDC to different numbers of ADCs and DACs having different speeds and resolutions makes it an ideal choice for analog test bus, mixed-mode boundary scan, and built-in self test applications. It combines the advantages of both analog test buses and boundary scan techniques while the area overhead of the proposed techniques is very low compared to the mixed-mode boundary scan techniques. RDC can save power by allowing the designer to program it as the right converter for desired application. This architecture can be potentially implemented inside a field programmable gate array (FPGA) to allow the FPGA communicate with the analog world. It can also be used as a stand-alone product to give flexibility to the user to choose ADC/DAC combinations for the desired application;Next, a new method for designing low power and small area ROMless direct digital frequency synthesizers (DDFSs) is presented. In this method, a non-linear digital-to-analog converter is used to replace the phase-to-sine amplitude ROM look-up table and the linear DAC in conventional DDFS. Since the non-linear DAC converts the phase information directly into analog sine wave, no phase-to-amplitude ROM look-up table is required;Finally, a new low voltage technique based on biased inverting opamp that can have almost rail-to-rail swing with continuously valid output is discussed. Based on this biasing technique, a 10-bit segmented R-2R DAC and an 8-bit successive approximation ADC are designed and presented

Energy-efficient data converter design in scaled CMOS technology

Data converters bridge the physical and digital worlds. They have been the crucial building blocks in modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT) and 5G communications. The applications raise energy-efficiency requirements for both low-speed and high-speed converters since they are widely deployed in wireless sensor nodes and portable devices. To explore the solutions, the author worked on three directions: 1) techniques to improve the efficiency of the low-speed converters including the comparator; 2) techniques to develop high-speed data converters including the reference stabilization; 3) new architecture to improve the efficiency of the capacitance-to-digital converter (CDC). In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator pre-amplifier (pre-amp) gain and results in higher noise. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain, thereby reducing noise and offset. Besides, statistical estimation and loading switching techniques are combined to further improve energy efficiency. A 40-nm CMOS prototype achieves a Walden FoM of 1.5 fJ/conversion-step while operating at 100-kS/s from a 0.5-V supply. To further improve the energy-efficiency of the comparator, a novel dynamic pre-amp is proposed. By using an inverter-based input pair powered by a floating reservoir capacitor, the pre-amp realizes both current reuse and dynamic bias, thereby significantly boosting g [subscript m] /I [subscript D] and reducing noise. Moreover, it greatly reduces the influence of the input common-mode (CM) voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180-nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under 1.2-V supply, which represents greater than 7 times energy efficiency boost compared to that of a Strong-Arm (SA) latch. The second part of this dissertation focuses on high-speed data converter techniques. A 10-bit high-speed two-stage loop-unrolled SAR ADC is presented. To reduce the SAR logic delay and power, each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. To suppress the comparator offset mismatch induced non-linearity, a shared pre-amp are employed in the second fine stage, which is implemented by a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55-dB peak SNDR at 200-MS/s sampling rate without any calibration. A key limiting factor for the SAR ADC to simultaneously achieve high speed and high resolution is the reference ripple settling problem caused by DAC switching. Unlike prior techniques that aim to minimize the reference ripple which requires large reference buffer power or on-chip decoupling capacitance area, this work proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. The prototype 10-bit 120-MS/s SAR ADC is fabricated in 40-nm CMOS process and achieves an SNDR of 55 dB with only 3 pF reference decoupling capacitor. Finally, this dissertation also presents the design of an incremental time-domain two-step CDC. Unlike the classic two-step CDC, this work replaces the OTA-based active-RC integrator with a VCO-based integrator and performs time domain (TD) ΔΣ modulation. The VCO is mostly digital and consumes low power. Featuring the infinite DC gain in phase domain and intrinsic spatial phase quantization, this TDΔΣ enables a CDC design, achieving 85-dB SQNR by having only a 4-bit quantizer, a 1st-order loop and a low OSR of 15. The prototype fabricated in 40-nm CMOS achieves a resolution of 0.29 fF while dissipating only 0.083 nJ per conversion, which improves the energy efficiency by greater than 2 times comparing to that of state-of-the-art CDCsElectrical and Computer Engineerin

Low power circuit design techniques for edge computing

In the booming era of Internet-of-Things (IoT), the trend of pushing inference from cloud to edge due to concerns of latency, bandwidth, and privacy has created a demand for energy-efficient edge computing devices. The edge computing devices have been the critical building blocks in modern electronic systems, supporting various applications such as neural network inference, mobile healthcare monitoring, and human-machine interface. To improve the energy efficiency of edge devices, the author worked in three directions: 1) developing a ternary neural network accelerator achieving higher energy-efficiency than state-of-the-art binary neural network; 2) developing a 4-bit neural network accelerator with one-shot ADC conversion for the entire MAC array; 3) a long-term, real-time muscle fatigue detection device with ultrathin, ultrasoft, and long-term stable dry epidermal electrodes. In the first part, we propose a mixed-signal ternary CNN-based processor featuring higher energy efficiency than BNN. It confers several key improvements: 1) the proposed ternary network provides 1.5-b resolution (0/+1/-1), leading to 3.9x OPs/inference reduction than BNN for the same MNIST accuracy; 2) a 1.5b multiply-and-accumulate (MAC) is implemented by VCM-based capacitor switching scheme, which inherently benefits from the reduced signal swing on the capacitive DAC (CDAC); 3) the VCM-based MAC introduces sparsity during training, resulting in lower switching rate. With a complete neural network on chip, the proposed design realizes 97.1% MNIST accuracy with only 0.18μJ per classification, presenting the highest power efficiency for comparable MNIST accuracy. The second part of this dissertation focuses on a 4-bit MAC macro. This work proposes a mixed-signal MAC macro that requires only 1 ADC operation for the entire 512 4b×4b MAC. This is achieved by mapping 9 partial products onto 5 wires based on their relative weights, dynamic buffering 5 wire voltages, and sampling them on properly sized SAR ADC capacitors. As a result, all MAC operations are finished in the charge domain by the end of the ADC sampling, allowing only 1 A/D conversion per multi-bit MAC. To further increase power efficiency, window-based comparison skipping and ReLU are embedded inside the SAR ADC, so that unnecessary comparison cycles are skipped for small or negative MAC outputs. Overall, despite using a 65nm process, the prototype chip achieves an energy efficiency of 164 TOPS/W for a 4-b MAC. Finally, this dissertation also presents a long-term, real-time muscle fatigue monitoring system consisting of 1) a hair-thin, skin-soft and mechanically robust e-tattoo electrode which is less susceptible to motion artifacts and capable of multi-day monitoring, 2) a battery-powered edge computing flexible printed circuit (FPC) which extracts instantaneous median frequency (IMDF) of surface electromyography (sEMG) bursts and wirelessly streams them to a mobile application. The system consumes an average of 33 mA current, supporting 25 hours of continuous operation, and could be extended into multiple days if only activated intermittently.Electrical and Computer Engineerin

High-speed Analog-to-digital Converters For Modern Satellite Receivers: Design Verification Test And Sensitivity Analysis

Mixed-signal System-on-chip devices such as analog-to-digital converters (ADCs) have become increasingly prevalent in the semiconductor industry. Since the complexity and applications are different for each device, complex testing and characterization methods are required. Specifically, signal integrity in I/O interfaces requires that standard RF design and test techniques must be integrated into mixed signal processes. While such techniques may be difficult to implement, on-chip test-vehicles and RF circuitry offer the possibility of wireless approaches to chip testing. This would eliminate expensive wafer probing solution to verify the design of high-speed ADC functionality currently required for high-speed product evaluation. This thesis describes a new high-speed analog-to-digital converter test methodology. The target systems used on-chip digital de-multiplexing and clock distribution. A detail sequence of performance testing operations is presented. Digital outputs are post processed and fed into a computer-aided ADC performance characterization tool which is custom-developed in a MATLAB GUI. The problems of high sampling rate ADC testing are described. The test methodologies described reduce test costs and overcome many test hardware limitations. As our focus is on satellite receiver systems, we emphasize the measurement of inter-modulation distortion and effective resolution bandwidth. As a primary characterization component, Fourier analysis is used and we address the issue of sample window adjustment to eliminate spectral leakage and false spur generation. A 6-bit 800 MSamples/sec dual channel SiGe-based ADC is used as a target example and investigated on the corner lot process variations to determine the impact of process variations and the sensitivity of the ADCs to critical process parameter variations

High speed data converter techniques

Moore's law not only applies to the semiconductor technology, it also applies to the Hard Disk Drive (HDD) system in the last 35 years. In order to meet the emerging demands of high performance computing application, HDD will continue to evolve in a very rapid pace. Very high speed analog-to-digital converters are demanded for Hard Disk Drive application.;FLASH architecture provides the highest speed using 2n-1 comparators to perform an n-bit conversion. In the extremes of speed, however, exotic technologies must still be used to achieve conversion rates beyond those obtained with a conventional silicon implementation. In this research, a four-way, time-interleaved flash ADC is demonstrated to achieve conversion speed up to 900MS/s using a 2.5v digital 0.25 micron bulk CMOS process. The maximum conversion rate practical with any technology is extended by the use of an array of well-matched flash ADCs. This technique trades off increased die area for increased speed in nearly one for one relationship but an reduced performance if the ADCs are not well matched in terms of gain, offset, nonlinearities and sampling skew. In the approach considered here, these problems are minimized by use of a simple method that ensures the individual ADC gain, offset and nonlinearities characteristics are inherently almost identical. A simple four phase clock generator is demonstrated which introduces only a small sampling skew. This scheme has been demonstrated in the comparatively simple 6-bit flash ADC case which achieved the highest acquisition speed of 900MS/s. Compared with the prior works, our work achieves higher SNDR at much higher analog input frequency at sampling frequency of 900MS/s. This same scheme may be applied to the first n-bits of a pipeline converter (or other converter method) enabling the same identical performance in the most significant bits.;In the second part of this dissertation, a new calibration principle with Voltage Controlled Resistors (VCR) for matched current sources is proposed. This technique can be used to produce multi copies of current units. Therefore, it is suitable for the calibration of high-resolution digital-to-analog converters that are based on equal current sources.</p

Amplifier and data converter techniques for low power sensor interfaces

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.Cataloged from PDF version of thesis.Includes bibliographical references (pages 151-157).Sensor interfaces circuits are integral components of wireless sensor nodes, and improvements to their energy-efficiency help enable long-term medical and industrial monitoring applications. This thesis explores both analog and algorithmic energy-saving techniques in the sensor interface signal chain. First, a data-dependent successive-approximation algorithm is developed and is demonstrated in a low-power analog-to-digital converter (ADC) implementation. When averaged over many samples, the energy per conversion and number of bitcycles per conversion used by this algorithm both scale logarithmically with the activity of the input signal, with each N-bit conversion using between 2 and 2N+1 bitcycles, compared to N for conventional binary SA. This algorithm reduces ADC power consumption when sampling signals with low mean activity, and its effectiveness is demonstrated on an electrocardiogram signal. With a 0.6V supply, the 10-bit ADC test chip has a maximum sample rate of 16 kHz and an effective number of bits (ENOB) of 9.73b. The ADC's Walden Figure of Merit (FoM) ranges from 3.5 to 20 fJ/conversion-step depending on the input signal activity. Second, an ultra-low supply voltage amplifier stage is developed and used to create an energy-efficient low-noise instrumentation amplifier (LNIA). This chopper LNIA uses a 0.2V-supply inverter-based input stage followed by a 0.8V-supply folded-cascode common-source stage. The high input-stage current needed to reduce the input-referred noise is drawn from the 0.2V supply, significantly reducing power consumption. The 0.8V stage provides high gain and signal swing, improving linearity. Biasing and common-mode rejection techniques for the 0.2V-stage are also presented. The analog front-end (AFE) test chip incorporating the chopper LNIA achieves a power-efficiency figure (PEF) of 1.6 with an input noise of 0.94 [mu]VRMS, integrated from 0.5 to 670 Hz. Human biopotential signals are measured using the AFE.by Frank M. Yaul.Ph. D

Design techniques for delta sigma modulators using VCO based ADCs

VCO-based ADCs have recently emerged as attractive alternative to conventional DeltaSigma (ΔΣ) modulator architectures. Few salient features of a VCObased ADC are: 1) the quantization noise is 1st order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are ideally suited for oversampled data converter techniques with the capability to operate at near GHz frequencies. However, their performance is severely limited by the non-linearity of the voltage to frequency transfer curve. Also, when operating at GHz frequencies, the excess loop delay (ELD) of a continuous-time ΔΣ modulator can be a large fraction of the sampling period, thereby affecting the of stability of the modulator. In this work,two new architectures are proposed to overcome the above mentioned drawbacks. In the first approach,a continuous-time Delta Sigma modulator incorporates a non-linear VCO as the second stage in a 2-stage residue canceling quantizer (RCQ) and mitigates the impact of its non-linearity by spanning only a small region of the VCOs tuning curve. In the second approach, both phase and frequency domain information are extracted from the VCO and fedback, which provides an extra clock cycle delay in the feeback path. This relaxes the timing constraints for the modulator, allowing it to be clocked at GHz frequencies