Hardware Security Implications of Reliability, Remanence and Recovery in Embedded Memory

Secure semiconductor devices usually destroy key material on tamper detection. However, data remanence effect in SRAM and Flash/EEPROM makes secure erasure process more challenging. On the other hand, data integrity of the embedded memory is essential to mitigate fault attacks and Trojan malware. Data retention issues could influence the reliability of embedded systems. Some examples of such issues in industrial and automotive applications are presented. When it comes to the security of semiconductor devices, both data remanence and data retention issues could lead to possible data recovery by an attacker. This paper introduces a new power glitching technique that reduces the data remanence time in embedded SRAM from seconds to microseconds at almost no cost. This would definitely help in designing systems with better secret key guarding. Data remanence in non-volatile memory could be influenced in the same way. The effect of data remanence and data retention on hardware security is discussed and possible countermeasures are suggested. This should raise awareness among the designers of secure embedded systems

Optimization of nanostructured permalloy electrodes for a lateral hybrid spin-valve structure

Ferromagnetic electrodes of a lateral semiconductor-based spin-valve structure are designed to provide a maximum of spin-polarized injection current. A single-domain state in remanence is a prerequisite obtained by nanostructuring Permalloy thin film electrodes. Three regimes of aspect ratios $m$ are identified by room temperature magnetic force microscopy: (i) high-aspect ratios of $m \ge 20$ provide the favored remanent single-domain magnetization states, (ii) medium-aspect ratios $m \sim 3$ to $m \sim 20$ yield highly remanent states with closure domains and (iii) low-aspect ratios of $m \le 3$ lead to multi-domain structures. Lateral kinks, introduced to bridge the gap between micro- and macroscale, disturb the uniform magnetization of electrodes with high- and medium-aspect ratios. However, vertical flanks help to maintain a uniformly magnetized state at the ferromagnet-semiconcuctor contact by domain wall pinning.Comment: revised version, major structural changes, figures reorganized,6 pages, 8 figures, revte

Radiation and temperature effects on electronic components investigated under the CSTI high capacity power project

The effects of nuclear radiation and high temperature environments must be fully known and understood for the electronic components and materials used in both the Power Conditioning and Control subsystem and the reactor Instrumentation and Control subsystem of future high capacity nuclear space power systems. This knowledge is required by the designer of these subsystems in order to develop highly reliable, long-life power systems for future NASA missions. A review and summary of the experimental results obtained for the electronic components and materials investigated under the power management element of the Civilian Space Technology Initiative (CSTI) high capacity power project are presented: (1) neutron, gamma ray, and temperature effects on power semiconductor switches, (2) temperature and frequency effects on soft magnetic materials; and (3) temperature effects on rare earth permanent magnets

Ion Irradiation Control of Ferromagnetism in (Ga,Mn)As

We report on a promising approach to the artificial modification of ferromagnetic properties in (Ga,Mn)As using a Ga$^+$ focused ion beam (FIB) technique. The ferromagnetic properties of (Ga,Mn)As such as magnetic anisotropy and Curie temperature can be controlled using Ga$^+$ ion irradiation, originating from a change in hole concentration and the corresponding systematic variation in exchange interaction between Mn spins. This change in hole concentration is also verified using micro-Raman spectroscopy. We envisage that this approach offers a means of modifying the ferromagnetic properties of magnetic semiconductors on the micro- or nano-meter scale.Comment: 4 pages, 4 figures, to appear in Jpn. J. Appl. Phys. (Part 2 Letters

Epitaxial Growth of an n-type Ferromagnetic Semiconductor CdCr2Se4 on GaAs(001) and GaP(001)

We report the epitaxial growth of CdCr2Se4, an n-type ferromagnetic semiconductor, on both GaAs and GaP(001) substrates, and describe the structural, magnetic and electronic properties. Magnetometry data confirm ferromagnetic order with a Curie temperature of 130 K, as in the bulk material. The magnetization exhibits hysteretic behavior with significant remanence, and an in-plane easy axis with a coercive field of ~125 Oe. Temperature dependent transport data show that the films are semiconducting in character and n-type as grown, with room temperature carrier concentrations of n ~ 1 x 10^18 cm-3.Comment: 12 pages, 3 figure

Analysis of Data Remanence and Power-up States of SRAM Cells in Embedded Systems

Contrary to popular assumption, Static RAM (SRAM), the main memory in most modern microcontrollers, temporarily retains its contents after power is lost. Instead of an immediate erase, SRAM data progressively degrades over a period (from milliseconds to several minutes at low temperatures) when power is cut o . This e ect, known as data remanence, is exploited by cold boot attacks, which are hardware-level threads that target encryption keys and other sensitive data stored in SRAM. On power-up, SRAM cells spontaneously set to unpredictable 0 or 1-states. These initial SRAM values describe a unique binary pattern that reveals a physical ngerprint of the device. Physical Unclonable Functions (PUFs) take advantage of this inherent process to obtain cryptographic keys or identi ers directly out of the chips, o ering a cost-e ective solution and a more secure alternative to conventional key-storage based on non-volatile memories. Moreover, SRAM power-up states may also be used as a source of randomness for True Random Number Generators (TRNGs). This Master's Thesis addresses these two security-related topics regarding SRAM modules in embedded systems. First, this project aims to investigate the vulnerability against cold-boot attacks of modern low-power devices, which is directly related to their low-temperature SRAM data remanence characteristics. Second, to assess the feasibility of implementing a PUF and a TRNG from SRAM power-up states. Both analyses consider the impact of temperature variations and are particularized for SRAM modules embedded in PIC18F4520 microcontrollers. Two sets of experiments are performed to generate the data required by both studies. The experimental setup and methodology are entirely designed and implemented within this project. The control of the execution of the experiments and the post-processing of the data are performed using MATLAB. Then, a set of metrics for characterizing SRAM data remanence are de ned, and a general methodology for SRAM-PUF and TRNG evaluation is established. The characterization of SRAM data remanence reveals that unprotected PIC18F4520 microcontrollers could be vulnerable to cold-boot attacks at temperatures below 0 C and that similar behaviour could be expected from same-range devices. The evaluation of the SRAM power-up states characteristics indicates that implementing an SRAM-PUF in PIC18F4520 microcontrollers could be feasible. In contrast, insu cient randomness appears to be contained in PIC18F4520 SRAM power-up states for a TRNG implementation to be viable in practic