DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability (DFT) logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers trade-off flexibility between test-application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase test quality when considering systematic variations. Through SPICE simulations, we show complete recovery of the test quality lost due to PDNs. The proposed method is robust sustaining 80.3% to 98.6% of the achieved test quality under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on test quality and offers a unified test solution for both ring and grid power gating styles

Leveraging CMOS Aging for Efficient Microelectronics Design

Aging is known to impact electronic systems affecting performance and reliability. However, it has been shown that it also brings benefits for power saving and area optimization. This paper presents highlights of those benefits and further shows how aging effects can be leveraged by novel methods to contribute towards improving hardware oriented security and reliability of electronic circuits. We have demonstrated static power reduction in complex circuits from IWLS05 benchmark suite, reaching a noticeable 7S% of reduction in ten years of operation. In hardware oriented security, a novel aging sensor has been proposed for detection of recycled ICs, measuring discharge time Tdv of the virtual power (VV dd ) network in power-gated designs. This sensor utilizes discharge time of VV dd network through leakage current that is much more sensitive to aging than path delay, exhibiting up to 15.7X increment in 10 years. Furthermore, we show how frequency degradation caused by aging is used for online prediction of remaining useful lifetime (RUL) of electronic circuits. Results show an average RUL prediction deviation of less than 0.1 years. This methodology provides node calculations rather than a mean time to failure (MTTF) of the population. The set of techniques that are presented in this paper takes advantage of aging effects, having a positive impact in various aspects of microelectronic systems