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Performance modelling and high performance buffer design for the system with network on chip
High performance novel dynamically allocated multi-queue (DAMQ) buffer schemes forsystems with network on chip (NoC) have been proposed and evaluated in this dissertation. Ananalytical model to predict performance of a NoC where wormhole switching technique andfully adaptive routing protocols has been developed and compared with simulations.In this dissertation, a novel analytical model for NoC which makes use of simple closeform calculations is presented. This model provides accurate network performance prediction inthe network stable region. The validity of this model is demonstrated by comparing analyticalprediction with simulation results obtained on high-radix k-ary 2-cube networks.Three novel switch buffer schemes, DAMQall, DAMQmin and DAMQshared, for system onchip with an interconnection network are also reported. The proposed schemes are based on aDAMQ self-compacting buffer hardware design. These schemes outperform existing approaches.DAMQall have similar performance using only half of the buffer size used in traditional SAMQimplementations. DAMQmin provides an excellent approach to optimize buffer managementproviding a good throughput when the network has a larger load. DAMQshared scheme lets virtualchannels from different physical channel share free buffer space. While providing similarperformance, DAMQshared scheme uses only around sixty percent of the buffer size that is used intraditional implementation for NoCs. In addition, using same size buffers, DAMQsharedoutperforms existing approaches such as SAMQ and DAMQall by 1% to 2% in throughput. Theproposed schemes also make a better utilization of the available buffer space