2 research outputs found

    Contention-Aware Mapping and Scheduling Optimization for NoC-Based MPSoCs (Student Abstract)

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    We consider spacial and temporal aspects of communication to avoid contention in Network-on-Chip (NoC) architectures. A constraint model is constructed such that the design concerns can be evaluated, and an efficient evolutionary algorithm with various heuristics is proposed to search for better solutions. Experimentations from random benchmarks demonstrate the efficiency of our method in multi-objective optimization and the effectiveness of our techniques in avoiding network contention

    Contention-Aware Mapping and Scheduling Optimization for NoC-Based MPSoCs (Student Abstract)

    No full text
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