Zuverlässigkeit digitaler Schaltungen unter Einfluss von intrinsischem Rauschen

Die kontinuierlich fortschreitende Miniaturisierung in integrierten Schaltungen führt zu einem Anstieg des intrinsischen Rauschens. Um den Einfluss von intrinsischem Rauschen auf die Zuverlässigkeit zukünftiger digitaler Schaltungen analysieren zu können, werden Methoden benötigt, die auf CAD-Verfahren wie Analogsimulation statt auf abschätzenden Berechnungen beruhen. Dieser Beitrag stellt eine neue Methode vor, die den Einfluss von intrinsischem Rauschen in digitalen Schaltungen für eine gegebene Prozesstechnologie analysieren kann. Die Amplituden von thermischen, 1/f und Schrotrauschen werden mit Hilfe eines SPICE Simulators bestimmt. Anschließend wird der Einfluss des Rauschens auf die Schaltungszuverlässigkeit durch Simulation analysiert. <br><br> Zusätzlich zur Analyse werden Möglichkeiten aufgezeigt, wie die durch Rauschen hervorgerufenen Effekte im Schaltungsentwurf mit berücksichtigt werden können. Im Gegensatz zum Stand der Technik kann die vorgestellte Methode auf beliebige Logikimplementierungen und Prozesstechnologien angewendet werden. Zusätzlich wird gezeigt, dass bisherige Ansätze den Einfluss von Rauschen bis um das Vierfache überschätzen

Quantifying Near-Threshold CMOS Circuit Robustness

In order to build energy efficient digital CMOS circuits, the supply voltage must be reduced to near-threshold. Problematically, due to random parameter variation, supply scaling reduces circuit robustness to noise. Moreover, the effects of parameter variation worsen as device dimensions diminish, further reducing robustness, and making parameter variation one of the most significant hurdles to continued CMOS scaling. This paper presents a new metric to quantify circuit robustness with respect to variation and noise along with an efficient method of calculation. The method relies on the statistical analysis of standard cells and memories resulting an an extremely compact representation of robustness data. With this metric and method of calculation, circuit robustness can be included alongside energy, delay, and area during circuit design and optimization

Low power, high performance pseudo-static D flip-flop

Digital systems, in particular microprocessor, have recently experienced phenomena growth in performance. Both technology advancement and clever design have sustained this performance growth. As clock frequency heads into the Ghz range, new circuit design, for both logic and storage, are needed. Such new circuit technology must provide needed performance with minimum power consumption. Flip-flops are essential elements of a digital system. They are used to hold both state information and results. As processor architecture such as superscalar becomes more advanced, the control logic grows more complex resulting in an increasing number of D flip-flops. These flip-flops are all driven by the global clock, which leads to higher power dissipation with increasing clock frequency. One way to reduce power consumption is to send the microprocessor into a sleep mode. Once in this mode, the clock is turned off (at logic low level), forcing the control logic to remain in a standby state. In this thesis, two D flip-flop designs are introduced and compared with conventional designs: dynamic NRC (no race condition) and pseudo-static cascode pull-down. Such design criteria comparisons include speed, power consumption, scaling, noise margin, and metastability

Harnessing resilience: biased voltage overscaling for probabilistic signal processing

A central component of modern computing is the idea that computation requires determinism. Contrary to this belief, the primary contribution of this work shows that useful computation can be accomplished in an error-prone fashion. Focusing on low-power computing and the increasing push toward energy conservation, the work seeks to sacrifice accuracy in exchange for energy savings. Probabilistic computing forms the basis for this error-prone computation by diverging from the requirement of determinism and allowing for randomness within computing. Implemented as probabilistic CMOS (PCMOS), the approach realizes enormous energy sav- ings in applications that require probability at an algorithmic level. Extending probabilistic computing to applications that are inherently deterministic, the biased voltage overscaling (BIVOS) technique presented here constrains the randomness introduced through PCMOS. Doing so, BIVOS is able to limit the magnitude of any resulting deviations and realizes energy savings with minimal impact to application quality. Implemented for a ripple-carry adder, array multiplier, and finite-impulse-response (FIR) filter; a BIVOS solution substantially reduces energy consumption and does so with im- proved error rates compared to an energy equivalent reduced-precision solution. When applied to H.264 video decoding, a BIVOS solution is able to achieve a 33.9% reduction in energy consumption while maintaining a peak-signal-to-noise ratio of 35.0dB (compared to 14.3dB for a comparable reduced-precision solution). While the work presented here focuses on a specific technology, the technique realized through BIVOS has far broader implications. It is the departure from the conventional mindset that useful computation requires determinism that represents the primary innovation of this work. With applicability to emerging and yet to be discovered technologies, BIVOS has the potential to contribute to computing in a variety of fashions.PhDCommittee Chair: Anderson, David; Committee Member: Conte, Thomas; Committee Member: Ferri, Bonnie; Committee Member: Hasler, Paul; Committee Member: Mooney, Vincen