Characterisation of silicon carbide CMOS devices for high temperature applications

PhD ThesisIn recent years it has become increasingly apparent that there is a large demand for resilient electronics that can operate within environments that standard silicon electronics cease to function such as high power and high voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This has become even more essential due to increased demands for sustainable energy production and the reduction in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive, energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for operation in such environments due to its advantageous electrical properties such as a high breakdown electric field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150 mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and high current power electronic devices, improving the already optimised silicon based structures. An important advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology has made a number of major steps forward over recent years and the commercial manufacturing process has advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise the potential of the material for electronic applications. This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature applications and fabricated with varying gate dielectric treatments and process steps. The influence of process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated by means of electrical characterisation and the results have been compared to theoretical models. The C-V and I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been employed in the design of the devices. The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility, which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most suitable treatment for a monolithic CMOS process. The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold voltage act to improve the device performance by acting to modify the charge at the interface or within the gate oxide and therefore increase the field effect mobility of the studied devices.Engineering and Physical Sciences Research Council (EPSRC) and Raytheon U

4H-SiC metal oxide semiconductor devices

PhD ThesisMetal oxide semiconductor (MOS) devices are the most important component in advanced integrated circuits (ICs). The success of Si in CMOS technology is owing to the excellent interface formed between Si and SiO2. However, Si-based electronic devices are not suitable to operate in high power, high frequency and high temperature conditions due to material limitations. 4H-SiC with a wide bandgap, high critical electric field, high thermal conductivity and high saturation drift velocity, is an attractive semiconductor material for extreme conditions. However, high quality oxide-semiconductor interfaces are still a major challenge in 4H-SiC MOS devices. This thesis focuses on interface studies of 4H-SiC MOS devices. The main aim is to produce high quality oxide/4H-SiC interfaces by the introduction of an ultrathin SiO2 layer between deposited oxides and 4H-SiC. Ultrathin SiO2 layers can be grown on 4H-SiC using a low thermal budget technique followed by Al2O3 deposition using ALD. N-type and p-type MOS capacitors were fabricated using a gate oxidation of 600 °C for 3 min, which produced SiO2 of thickness 0.7 nm as estimated using ARXPS. Electrical characterisation demonstrates an interface trap density (Dit) of 4-6 × 1011 cm-2eV-1 at 0.2 eV from the conduction and valence band edges. This represents a reduction in Dit by 1-2 orders of magnitude compared to the devices fabricated at 1150 °C for 180 min in the furnace. Furthermore, field effect channel mobility as high as 125 cm2/V.s and a subthreshold slope of 130 mV/dec were obtained from MOSFETs using similar gate stacks. The mobility of MOSFETs decreases with increasing temperature indicating that the electron conductivity is limited by phonon scattering rather than Coulomb scattering, and proves that Dit at the oxide/4H-SiC has been reduced. The ultrathin layer is believed to be a good interface layer between Al2O3 and 4H-SiC. As the temperature and time of the oxidation process increased, resulting in thicker SiO2, the values of Dit increased for both p-type and n-type MOS capacitors. Ultrathin SiO2 layers were also grown underneath a deposited SiO2 layer by N2O annealing at 1175 °C. From n-type MOS capacitor results, the lowest values of Dit obtained were 1.7 × 1012 cm-2eV-1 at 0.2 eV below the conduction band edge, for gate oxides consisting of 60 nm deposited SiO2 followed by 90 min of N2O annealing. This process produced a SiO2 layer 0.68 nm thick, estimated using the Deal-Grove model. The values of Dit increased as the grown SiO2 thicknesses became thicker or thinner than 0.68 nm. This trend is similar to what ii was found in ultrathin SiO2/Al2O3 gate stacks of MOS capacitors proving that 0.7 nm thick is the best thickness of SiO2 to use for 4H-SiC MOS devices. Electrical measurement up to 300 °C proved that these fabricated MOS devices are able to operate well at high temperature. MOSFETs utilizing ultrathin SiO2/Al2O3 gate stacks could retain their enhancement mode behaviour even at high temperature demonstrating the devices capability to be operated in extreme conditions. Both gate stacks also exhibited a low leakage current and were able to withstand electric fields far above 3 MV/cm, which is needed for actual operating system. The scope of these findings points to solutions for the interface challenges in 4H-SiC MOS devices. A thermally grown SiO2 layer 0.7 nm thick exhibited the lowest Dit values for both gate stacks and also produced high field effect channel mobility in MOSFETs. It is anticipated that this fabrication approach will mitigate the oxide/4H-SiC interface problem and contribute towards the development of improved power electronic devices.Ministry of Education Malaysia (MOHE) and in part by the Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka for financially sponsored my study through SLAI scholarship. Special thanks to Engineering and Physical Sciences Research Council (EPSRC), UK for providing the financial support to carry out this research