Soft-error resilient on-chip memory structures

Soft errors induced by energetic particle strikes in on-chip memory structures, such as L1 data/instruction caches and register files, have become an increasing challenge in designing new generation reliable microprocessors. Due to their transient/random nature, soft errors cannot be captured by traditional verification and testing process due to the irrelevancy to the correctness of the logic. This dissertation is thus focusing on the reliability characterization and cost-effective reliable design of on-chip memories against soft errors. Due to various performance, area/size, and energy constraints in various target systems, many existing unoptimized protection schemes on cache memories may eventually prove significantly inadequate and ineffective. This work develops new lifetime models for data and tag arrays residing in both the data and instruction caches. These models facilitate the characterization of cache vulnerability of the stored items at various lifetime phases. The design methodology is further exemplified by the proposed reliability schemes targeting at specific vulnerable phases. Benchmarking is carried out to showcase the effectiveness of these approaches. The tag array demands high reliability against soft errors while the data array is fully protected in on-chip caches, because of its crucial importance to the correctness of cache accesses. Exploiting the address locality of memory accesses, this work proposes a Tag Replication Buffer (TRB) to protect information integrity of the tag array in the data cache with low performance, energy and area overheads. To provide a comprehensive evaluation of the tag array reliability, this work also proposes a refined evaluation metric, detected-without-replica-TVF (DOR-TVF), which combines the TVF and access-with-replica (AWR) analysis. Based on the DOR-TVF analysis, a TRB scheme with early write-back (TRB-EWB) is proposed, which achieves a zero DOR-TVF at a negligible performance overhead. Recent research, as well as the proposed optimization schemes in this cache vulnerability study, have focused on the design of cost-effective reliable data caches in terms of performance, energy, and area overheads based on the assumption of fixed error rates. However, for systems in operating environments that vary with time or location, those schemes will be either insufficient or over-designed for the changing error rates. This work explores the design of a self-adaptive reliable data cache that dynamically adapts its employed reliability schemes to the changing operating environments in order to maintain a target reliability. The experimental evaluation shows that the self-adaptive data cache achieves similar reliability to a cache protected by the most reliable scheme, while simultaneously minimizing the performance and power overheads. Besides the data/instruction caches, protecting the register file and its data buses is crucial to reliable computing in high-performance microprocessors. Since the register file is in the critical path of the processor pipeline, any reliable design that increases either the pressure on the register file or the register file access latency is not desirable. This work proposes to exploit narrow-width register values, which represent the majority of generated values, for making the duplicates within the same register data item. A detailed architectural vulnerability factor (AVF) analysis shows that this in-register duplication (IRD) scheme significantly reduces the AVF in the register file compared to the conventional design. The experimental evaluation also shows that IRD provides superior read-with-duplicate (RWD) and error detection/recovery rates under heavy error injection as compared to previous reliability schemes, while only incurring a small power overhead. By integrating the proposed reliable designs in data/instruction caches and register files, the vulnerability of the entire microprocessor is dramatically reduced. The new lifetime model, the self-adaptive design and the narrow-width value duplication scheme proposed in this work can also provide guidance to architects toward highly efficient reliable system design

Évaluation des effets des neutrons atmosphériques sur l'électronique embarqué en avionique et recherche de solutions de durcissement

Cette thèse s intéresse aux effets des particules présentent naturellement dans l atmosphère. L'étude se focalise principalement sur l'impact des neutrons sur des composants électroniques fortement intégrés. La première partie détaille l'environnement radiatif naturel ainsi que les moyens de tests existants. Les technique de test sous faisceau laser sont mise en avant. La seconde partie s intéresse au développement d'une plateforme de test de mémoires à base de FPGA programmée en VHDL. Les conceptions matérielle et logicielle sont explicitées. Une plateforme de test pour microprocesseur est également présentée. La dernière partie traite de l'évaluation de la sensibilité d'une mémoire SRAM bulk 90 nm sous faisceau laser 1064 nm. Le décodage de son plan mémoire est effectué et des solutions de durcissement sont suggéréesThis thesis highlights the effects of natural atmospheric particles. The study mainly focuses on the neutrons impact on highly integrated electronic component. The first part deals with the natural radiative environment and the tests facility. Laser beams facilities are point out. The second part explains the devlopment of a memory test platform which is based on a FPGA and programmed with VHDL. Hardware and software designs are detailed. A microprocessor test platform is presented too. The last part deals with the sensibility evaluation of a 90 nm bulk SRAM memory under a 1064 nm laser. The descrambling of the memory is explained and hardening solutions are proposedBORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF