Generalized Fast-Convolution-based Filtered-OFDM: Techniques and Application to 5G New Radio

This paper proposes a generalized model and methods for fast-convolution (FC)-based waveform generation and processing with specific applications to fifth generation new radio (5G-NR). Following the progress of 5G-NR standardization in 3rd generation partnership project (3GPP), the main focus is on subband-filtered cyclic prefix (CP) orthogonal frequency-division multiplexing (OFDM) processing with specific emphasis on spectrally well localized transmitter processing. Subband filtering is able to suppress the interference leakage between adjacent subbands, thus supporting different numerologies for so-called bandwidth parts as well as asynchronous multiple access. The proposed generalized FC scheme effectively combines overlapped block processing with time- and frequency-domain windowing to provide highly selective subband filtering with very low intrinsic interference level. Jointly optimized multi-window designs with different allocation sizes and design parameters are compared in terms of interference levels and implementation complexity. The proposed methods are shown to clearly outperform the existing state-of-the-art windowing and filtering-based methods.Comment: To appear in IEEE Transactions on Signal Processin

Efficient Fast-Convolution-Based Waveform Processing for 5G Physical Layer

This paper investigates the application of fast-convolution (FC) filtering schemes for flexible and effective waveform generation and processing in the fifth generation (5G) systems. FC-based filtering is presented as a generic multimode waveform processing engine while, following the progress of 5G new radio standardization in the Third-Generation Partnership Project, the main focus is on efficient generation and processing of subband-filtered cyclic prefix orthogonal frequency-division multiplexing (CP-OFDM) signals. First, a matrix model for analyzing FC filter processing responses is presented and used for designing optimized multiplexing of filtered groups of CP-OFDM physical resource blocks (PRBs) in a spectrally well-localized manner, i.e., with narrow guardbands. Subband filtering is able to suppress interference leakage between adjacent subbands, thus supporting independent waveform parametrization and different numerologies for different groups of PRBs, as well as asynchronous multiuser operation in uplink. These are central ingredients in the 5G waveform developments, particularly at sub-6-GHz bands. The FC filter optimization criterion is passband error vector magnitude minimization subject to a given subband band-limitation constraint. Optimized designs with different guardband widths, PRB group sizes, and essential design parameters are compared in terms of interference levels and implementation complexity. Finally, extensive coded 5G radio link simulation results are presented to compare the proposed approach with other subband-filtered CP-OFDM schemes and time-domain windowing methods, considering cases with different numerologies or asynchronous transmissions in adjacent subbands. Also the feasibility of using independent transmitter and receiver processing for CP-OFDM spectrum control is demonstrated

Modeling of Orthogonal Frequency Division Multiplexing (OFDM) for Transmission in Broadband Wireless Communications

Orthogonal Frequency Division Multiplexing (OFDM) is a multi carrier modulation technique that provides high bandwidth efficiency because the carriers are orthogonal to each other and multiple carriers share the data among themselves. The main advantage of this transmission technique is its robustness to channel fading in wireless communication environment. This paper investigates the effectiveness of OFDM and assesses its suitability as a modulation technique in wireless communications. Several of the main factors affecting the performance of a typical OFDM system are considered and they include multipath delay spread, channel noise, distortion (clipping), and timing requirements. The core processing block and performance analysis of the system is modeled usingMatlab

Design And Implementation Of Radix-4 Fast Fourier Transform In Asia Chip With 0.18 M Standard CMOS Technology [TK5102.9. S624 2008 f rb].

Jelmaan Fourier pantas (FFT) merupakan blok yang penting dan digunakan secara meluas dalam algoritma pemprosesan isyarat digital. The Fast Fourier Transform (FFT) is a critical block and widely used in digital signal processing algorithm

Acceleration Techniques for Sparse Recovery Based Plane-wave Decomposition of a Sound Field

Plane-wave decomposition by sparse recovery is a reliable and accurate technique for plane-wave decomposition which can be used for source localization, beamforming, etc. In this work, we introduce techniques to accelerate the plane-wave decomposition by sparse recovery. The method consists of two main algorithms which are spherical Fourier transformation (SFT) and sparse recovery. Comparing the two algorithms, the sparse recovery is the most computationally intensive. We implement the SFT on an FPGA and the sparse recovery on a multithreaded computing platform. Then the multithreaded computing platform could be fully utilized for the sparse recovery. On the other hand, implementing the SFT on an FPGA helps to flexibly integrate the microphones and improve the portability of the microphone array. For implementing the SFT on an FPGA, we develop a scalable FPGA design model that enables the quick design of the SFT architecture on FPGAs. The model considers the number of microphones, the number of SFT channels and the cost of the FPGA and provides the design of a resource optimized and cost-effective FPGA architecture as the output. Then we investigate the performance of the sparse recovery algorithm executed on various multithreaded computing platforms (i.e., chip-multiprocessor, multiprocessor, GPU, manycore). Finally, we investigate the influence of modifying the dictionary size on the computational performance and the accuracy of the sparse recovery algorithms. We introduce novel sparse-recovery techniques which use non-uniform dictionaries to improve the performance of the sparse recovery on a parallel architecture

Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Many critical EDA problems suffer from the curse of dimensionality, i.e. the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g. full-chip routing/placement and circuit sizing), or extensive process variations (e.g. variability/reliability analysis and design for manufacturability). The computational challenges generated by such high dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents "tensor computation" as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and System

FPGA implementations for parallel multidimensional filtering algorithms

PhD ThesisOne and multi dimensional raw data collections introduce noise and artifacts, which need to be recovered from degradations by an automated filtering system before, further machine analysis. The need for automating wide-ranged filtering applications necessitates the design of generic filtering architectures, together with the development of multidimensional and extensive convolution operators. Consequently, the aim of this thesis is to investigate the problem of automated construction of a generic parallel filtering system. Serving this goal, performance-efficient FPGA implementation architectures are developed to realize parallel one/multi-dimensional filtering algorithms. The proposed generic architectures provide a mechanism for fast FPGA prototyping of high performance computations to obtain efficiently implemented performance indices of area, speed, dynamic power, throughput and computation rates, as a complete package. These parallel filtering algorithms and their automated generic architectures tackle the major bottlenecks and limitations of existing multiprocessor systems in wordlength, input data segmentation, boundary conditions as well as inter-processor communications, in order to support high data throughput real-time applications of low-power architectures using a Xilinx Virtex-6 FPGA board. For one-dimensional raw signal filtering case, mathematical model and architectural development of the generalized parallel 1-D filtering algorithms are presented using the 1-D block filtering method. Five generic architectures are implemented on a Virtex-6 ML605 board, evaluated and compared. A complete set of results on area, speed, power, throughput and computation rates are obtained and discussed as performance indices for the 1-D convolution architectures. A successful application of parallel 1-D cross-correlation is demonstrated. For two dimensional greyscale/colour image processing cases, new parallel 2-D/3-D filtering algorithms are presented and mathematically modelled using input decimation and output image reconstruction by interpolation. Ten generic architectures are implemented on the Virtex-6 ML605 board, evaluated and compared. Key results on area, speed, power, throughput and computation rate are obtained and discussed as performance indices for the 2-D convolution architectures. 2-D image reconfigurable processors are developed and implemented using single, dual and quad MAC FIR units. 3-D Colour image processors are devised to act as 3-D colour filtering engines. A 2-D cross-correlator parallel engine is successfully developed as a parallel 2-D matched filtering algorithm for locating any MRI slice within a MRI data stack library. Twelve 3-D MRI filtering operators are plugged in and adapted to be suitable for biomedical imaging, including 3-D edge operators and 3-D noise smoothing operators. Since three dimensional greyscale/colour volumetric image applications are computationally intensive, a new parallel 3-D/4-D filtering algorithm is presented and mathematically modelled using volumetric data image segmentation by decimation and output reconstruction by interpolation, after simultaneously and independently performing 3-D filtering. Eight generic architectures are developed and implemented on the Virtex-6 board, including 3-D spatial and FFT convolution architectures. Fourteen 3-D MRI filtering operators are plugged and adapted for this particular biomedical imaging application, including 3-D edge operators and 3-D noise smoothing operators. Three successful applications are presented in 4-D colour MRI (fMRI) filtering processors, k-space MRI volume data filter and 3-D cross-correlator.IRAQI Government