3 research outputs found
Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems
With the increasing digital services demand, performance and power-efficiency
become vital requirements for digital circuits and systems. However, the
enabling CMOS technology scaling has been facing significant challenges of
device uncertainties, such as process, voltage, and temperature variations. To
ensure system reliability, worst-case corner assumptions are usually made in
each design level. However, the over-pessimistic worst-case margin leads to
unnecessary power waste and performance loss as high as 2.2x. Since
optimizations are traditionally confined to each specific level, those safe
margins can hardly be properly exploited.
To tackle the challenge, it is therefore advised in this Ph.D. thesis to
perform a cross-layer optimization for digital signal processing circuits and
systems, to achieve a global balance of power consumption and output quality.
To conclude, the traditional over-pessimistic worst-case approach leads to
huge power waste. In contrast, the adaptive voltage scaling approach saves
power (25% for the CORDIC application) by providing a just-needed supply
voltage. The power saving is maximized (46% for CORDIC) when a more aggressive
voltage over-scaling scheme is applied. These sparsely occurred circuit errors
produced by aggressive voltage over-scaling are mitigated by higher level error
resilient designs. For functions like FFT and CORDIC, smart error mitigation
schemes were proposed to enhance reliability (soft-errors and timing-errors,
respectively). Applications like Massive MIMO systems are robust against lower
level errors, thanks to the intrinsically redundant antennas. This property
makes it applicable to embrace digital hardware that trades quality for power
savings.Comment: 190 page
Computation-skip error resilient scheme for recursive CORDIC
Aggressive voltage and frequency scaling are widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical voltage or frequency results to numerous timing errors, and hence unacceptable output quality. In this paper, a computation-skip (CS) scheme is proposed for recursive digital signal processors with a fixed cycles per instruction (CPI) to correct timing errors. A CORDIC processor with the proposed CS scheme still functions when scaling beyond the sub-critical voltage or frequency. It improves EVM by 47.9 dB at its most
critical frequency or supply voltage, and extends the voltage scaling limit by 90 mV w.r.t the conventional CORDIC. Besides, it is more than 1.7X energy efficient w.r.t. the conventional highspeed CORDIC, which is designed for a more aggressive scaling.status: publishe