2 research outputs found

    High Speed Camera Chip

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    abstract: The market for high speed camera chips, or image sensors, has experienced rapid growth over the past decades owing to its broad application space in security, biomedical equipment, and mobile devices. CMOS (complementary metal-oxide-semiconductor) technology has significantly improved the performance of the high speed camera chip by enabling the monolithic integration of pixel circuits and on-chip analog-to-digital conversion. However, for low light intensity applications, many CMOS image sensors have a sub-optimum dynamic range, particularly in high speed operation. Thus the requirements for a sensor to have a high frame rate and high fill factor is attracting more attention. Another drawback for the high speed camera chip is its high power demands due to its high operating frequency. Therefore, a CMOS image sensor with high frame rate, high fill factor, high voltage range and low power is difficult to realize. This thesis presents the design of pixel circuit, the pixel array and column readout chain for a high speed camera chip. An integrated PN (positive-negative) junction photodiode and an accompanying ten transistor pixel circuit are implemented using a 0.18 µm CMOS technology. Multiple methods are applied to minimize the subthreshold currents, which is critical for low light detection. A layout sharing technique is used to increase the fill factor to 64.63%. Four programmable gain amplifiers (PGAs) and 10-bit pipeline analog-to-digital converters (ADCs) are added to complete on-chip analog to digital conversion. The simulation results of extracted circuit indicate ENOB (effective number of bits) is greater than 8 bits with FoM (figures of merit) =0.789. The minimum detectable voltage level is determined to be 470μV based on noise analysis. The total power consumption of PGA and ADC is 8.2mW for each conversion. The whole camera chip reaches 10508 frames per second (fps) at full resolution with 3.1mm x 3.4mm area.Dissertation/ThesisMasters Thesis Electrical Engineering 201

    A study of mobile robot motion planning

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    This thesis studies motion planning for mobile robots in various environments. The basic tools for the research are the configuration space and the visibility graph. A new approach is developed which generates a smoothed minimum time path. The difference between this and the Minimum Time Path at Visibility Node (MTPVN) is that there is more clearance between the robot and the obstacles, and so it is safer. The accessibility graph plays an important role in motion planning for a massless mobile robot in dynamic environments. It can generate a minimum time motion in 0(n2»log(n)) computation time, where n is the number of vertices of all the polygonal obstacles. If the robot is not considered to be massless (that is, it requires time to accelerate), the space time approach becomes a 3D problem which requires exponential time and memory. A new approach is presented here based on the improved accessibility polygon and improved accessibility graph, which generates a minimum time motion for a mobile robot with mass in O((n+k)2»log(n+k)) time, where n is the number of vertices of the obstacles and k is the number of obstacles. Since k is much less than n, so the computation time for this approach is almost the same as the accessibility graph approach. The accessibility graph approach is extended to solve motion planning for robots in three dimensional environments. The three dimensional accessibility graph is constructed based on the concept of the accessibility polyhedron. Based on the properties of minimum time motion, an approach is proposed to search the three dimensional accessibility graph to generate the minimum time motion. Motion planning in binary image representation environment is also studied. Fuzzy logic based digital image processing has been studied. The concept of Fuzzy Principal Index Of Area Coverage (PIOAC) is proposed to recognise and match objects in consecutive images. Experiments show that PIOAC is useful in recognising objects. The visibility graph of a binary image representation environment is very inefficient, so the approach usually used to plan the motion for such an environment is the quadtree approach. In this research, polygonizing an obstacle is proposed. The approaches developed for various environments can be used to solve the motion planning problem without any modification. A simulation system is designed to simulate the approaches
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