Transceiver design and system optimization for ultra-wideband communications

This dissertation investigates the potential promises and proposes possible solutions to the challenges of designing transceivers and optimizing system parameters in ultra-wideband (UWB) systems. The goal is to provide guidelines for UWB transceiver implementations under constraints by regulation, existing interference, and channel estimation. New UWB pulse shapes are invented that satisfy the Federal Communications Commission spectral mask. Parameters are designed to possibly implement the proposed pulses. A link budget is quantified based on an accurate frequency-dependent path loss calculation to account for variations across the ultra-wide bandwidth of the signal. Achievable information rates are quantified as a function of transmission distance over additive white Gaussian noise and multipath channels under specific UWB constraints: limited power spectral density, specific modulation formats, and a highly dispersive channel. The effect of self-interference (SI) and inter-symbol interference (ISI) on channel capacity is determined, and modulation formats that mitigate against this effect is identified. Spreading gains of familiar UWB signaling formats are evaluated, and UWB signals are proved to be spread spectrum. Conditions are formulated for trading coding gain with spreading gain with only a small impact on performance. Numerical results are examined to demonstrate that over a frequency-selective channel, the spreading gain may be beneficial in reducing the SI and ISI resulting in higher information rates. A reduced-rank adaptive filtering technique is applied to the problem of interference suppression and optimum combining in UWB communications. The reduced-rank combining method, in particular the eigencanceler, is proposed and compared with a minimum mean square error Rake receiver. Simulation results are evaluated to show that the performance of the proposed method is superior to the minimum mean square error when the correlation matrix is estimated from limited data. Impact of channel estimation on UWB system performance is investigated when path delays and path amplitudes are jointly estimated. Cramér-Rao bound (CRB) expressions for the variance of path delay and amplitude estimates are formulated using maximum likelihood estimation. Using the errors obtained from the CRB, the effective signal-to-noise ratio for UWB Rake receivers employing maximum ratio combining (MRC) is devised in the presence of channel path delay and amplitude errors. An exact expression of the bit error rate (BER) for UWB Rake receivers with MRC is derived with imperfect estimates of channel path delays and amplitudes. Further, this analysis is applied to design optimal transceiver parameters. The BER is used as part of a binary symmetric channel and the achievable information rates are evaluated. The optimum power allocation and number of symbols allocated to the pilot are developed with respect to maximizing the information rate. The optimal signal bandwidth to be used for UWB communications is determined in the presence of imperfect channel state information. The number of multipath components to be collected by Rake receivers is designed to optimize performance with non-ideal channel estimation

Energy-efficient analog-to-digital conversion for ultra-wideband radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 207-222).In energy constrained signal processing and communication systems, a focus on the analog or digital circuits in isolation cannot achieve the minimum power consumption. Furthermore, in advanced technologies with significant variation, yield is traditionally achieved only through conservative design and a sacrifice of energy efficiency. In this thesis, these limitations are addressed with both a comprehensive mixed-signal design methodology and new circuits and architectures, as presented in the context of an analog-to-digital converter (ADC) for ultra-wideband (UWB) radio. UWB is an emerging technology capable of high-data-rate wireless communication and precise locationing, and it requires high-speed (>500MS/s), low-resolution ADCs. The successive approximation register (SAR) topology exhibits significantly reduced complexity compared to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network enable the high-speed operation. Finally, only a small amount of redundancy, with negligible power penalty, dramatically improves the yield of the highly parallel ADC in deep sub-micron CMOS.by Brian P. Ginsburg.Ph.D

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process