Analysis and Evaluation of End-to-End PTP Synchronization for Ethernet-based Fronthaul

Provisioning of cost-effective Ethernet-based fronthaul by reusing the LAN infrastructure available in most commercial buildings is challenging predominantly in terms of the required bandwidth and synchronization. In contrast to a synchronous fronthaul, a PTP-based Ethernet network must cope with estimation noise introduced by packet delay variation (PDV) for synchronization recovery. The SYNC packet used for PTP on such networks is expected to suffer from significant PDV due to the fronthaul traffic and other background traffic. Further challenge is when the involved network switches do not support PTP and therefore synchronization can only be done by end-devices. Focusing on this scenario, this paper analyzes the problems that may affect the time-offset estimation accuracy and presents schemes to mitigate these problems. The performance is evaluated through a self-developed FPGA-based testbed and the results suggest that the end-to-end PTP approach can fulfill the less strict time alignment requirements of 3GPP standards if PDV is handled properly

Clock synchronisation for UWB and DECT communication networks

Synchronisation deals with the distribution of time and/or frequency across a network of nodes dispersed in an area, in order to align their clocks with respect to time and/or frequency. It remains an important requirement in telecommunication networks, especially in Time Division Duplexing (TDD) systems such as Ultra Wideband (UWB) and Digital Enhanced Cordless Telecommunications (DECT) systems. This thesis explores three di erent research areas related to clock synchronisation in communication networks; namely algorithm development and implementation, managing Packet Delay Variation (PDV), and coping with the failure of a master node. The first area proposes a higher-layer synchronisation algorithm in order to meet the specific requirements of a UWB network that is based on the European Computer Manufacturers Association (ECMA) standard. At up to 480 Mbps data rate, UWB is an attractive technology for multimedia streaming. Higher-layer synchronisation is needed in order to facilitate synchronised playback at the receivers and prevent distortion, but no algorithm is de ned in the ECMA-368 standard. In this research area, a higher-layer synchronisation algorithm is developed for an ECMA-368 UWB network. Network simulations and FPGA implementation are used to show that the new algorithm satis es the requirements of the network. The next research area looks at how PDV can be managed when Precision Time Protocol (PTP) is implemented in an existing Ethernet network. Existing literature indicates that the performance of a PDV ltering algorithm usually depends on the delay pro le of the network in which it is applied. In this research area, a new sample-mode PDV filter is proposed which is independent of the shape of the delay profile. Numerical simulations show that the sample-mode filtering algorithm is able to match or out-perform the existing sample minimum, mean, and maximum filters, at differentlevels of network load. Finally, the thesis considers the problem of dealing with master failures in a PTP network for a DECT audio application. It describes the existing master redundancy techniques and shows why they are unsuitable for the specific application. Then a new alternate master cluster technique is proposed along with an alternative BMCA to suit the application under consideration. Network simulations are used to show how this technique leads to a reduction in the total time to recover from a master failure

A Survey of Clock Synchronization Over Packet-Switched Networks

Clock synchronization is a prerequisite for the realization of emerging applications in various domains such as industrial automation and the intelligent power grid. This paper surveys the standardized protocols and technologies for providing synchronization of devices connected by packet-switched networks. A review of synchronization impairments and the state-of-the-art mechanisms to improve the synchronization accuracy is then presented. Providing microsecond to sub-microsecond synchronization accuracy under the presence of asymmetric delays in a cost-effective manner is a challenging problem, and still an open issue in many application scenarios. Further, security is of significant importance for systems where timing is critical. The security threats and solutions to protect exchanged synchronization messages are also discussed