Automated CNC Micromachining for Integrated THz Waveguide Circuits

Computer Numerically Controlled (CNC) machining of splitblock waveguide circuits has become the primary method of constructing terahertz waveguide circuits. The majority of these circuits have been made on traditional CNC machining centers or on custom-made laboratory machining systems. At both the University of Arizona and Arizona State University, we have developed techniques for machining splitblock waveguide circuits using purpose-built ultra high precision CNC machining centers designed for micromachining. These systems combine the automation of a traditional CNC machining center, including a high capacity toolchanger, workpiece and tool metrology systems and a large work volume, with the precision of custom laboratory systems. The systems at UofA and ASU are built by Kern Micro and deliver typical measured dimensional accuracies of 2-3 microns. Waveguide surface finish has been measured with a Veeco white light interferometric microscope to be Ra~75 nm. Tools of sizes between 25 microns and 10mm are available, with toolchanger capacities of 24-32 tools

Confirming the Signal Integrity in Transmission of Digital Signals on Microstrip Straight Circuits via the Eye Diagrams

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the speeds on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book 2-D Electromagnetic Simulation of Passive Microstrip Circuits from the corresponding author of this paper

Advanced electrode models and numerical modelling for high frequency Electrical Impedance Tomography systems

The thesis discusses various electrode models and finite element analysis methods for Electrical Impedance Tomography (EIT) systems. EIT is a technique for determining the distribution of the conductivity or admittivity in a volume by injecting electrical currents into the volume and measuring the corresponding potentials on the surface of the volume. Various electrode models were investigated for operating EIT systems at higher frequencies in the beta-dispersion band. Research has shown that EIT is potentially capable to distinguish malignant and benign tumours in this frequency band. My study concludes that instrumental effects of the electrodes and full Maxwell effects of EIT systems are the major issues, and they have to be addressed when the operating frequency increases. In the thesis, I proposed 1) an Instrumental Electrode Model (IEM) for the quasi-static EIT formula, based on the analysis of the hardware structures attached to electrodes; 2) a Complete Electrode Model based on Impedance Boundary Conditions (CEM-IBC) that introduces the contact impedances into the full Maxwell EIT formula; 3) a Transmission line Port Model (TPM) for electrode pairs with the instrumental effects, the contact impedance, and the full Maxwell effects considered for EIT systems. Circuit analysis, Partial Differential Equations (PDE) analysis, numerical analysis and finite element methods were used to develop the models. The results obtained by the proposed models are compared with widely used Commercial PDE solvers. This thesis addresses the two major problems (instrumental effects of the electrodes and full Maxwell effects of EIT systems) with the proposed advanced electrode models. Numerical experiments show that the proposed models are more accurate in the high frequency range of EIT systems. The proposed electrode models can be also applicable to inverse problems, and the results show promising. Simple hardware circuits for verifying the results experimentally have been also designed

Dimensional hybridity in measurement-induced criticality

Entanglement transitions in quantum dynamics present a novel class of phase transitions in non-equilibrium systems. When a many-body quantum system undergoes hybrid quantum dynamics, consisting of unitary evolution interspersed with monitored random measurements, the steady-state can exhibit a phase transition between volume- and area-law entanglement. The role of dimension in the nature of these transitions is an open problem. There is a dimensional correspondence between measurement-induced transitions in non-unitary quantum circuits in $d$ spatial dimensions and classical statistical mechanical models in $d+1$ dimensions, where the time dimension in the quantum problem is mapped to a spatial dimension in the classical model. In this work we show that the role of dimension is considerably richer by unveiling a form of `dimensional hybridity': critical properties of the steady-state entanglement are governed by a combination of exponents consistent with $d$-dimensional percolation and $(d+1)$-dimensional percolation. We uncover this dimensional hybridity in 1+1D and 2+1D circuits using a graph-state based simulation algorithm where the entanglement structure is encoded in an underlying graph, providing access to the geometric structure of entanglement. We locate the critical point using the tripartite information, revealing area-law entanglement scaling at criticality, and showing that the entanglement transition coincides with the purification transition. The emergence of this `dimensional hybridity' in these non-unitary quantum circuits sheds new light on the universality of measurement-induced transitions, and opens the way for analyzing the quantum error correcting properties of random unitary circuits in higher dimensions.Comment: 17 pages, 15 figures. Updated estimates of surface exponents $\eta_\parallel$ and $\eta_\bot

Indicating Asynchronous Array Multipliers

Multiplication is an important arithmetic operation that is frequently encountered in microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of many indicating asynchronous array multipliers, which are inherently elastic and modular and are robust to timing, process and parametric variations. We consider the physical realization of many indicating asynchronous array multipliers using a 32/28nm CMOS technology. The weak-indication array multipliers comprise strong-indication or weak-indication full adders, and strong-indication 2-input AND functions to realize the partial products. The multipliers were synthesized in a semi-custom ASIC design style using standard library cells including a custom-designed 2-input C-element. 4x4 and 8x8 multiplication operations were considered for the physical implementations. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols were utilized for data communication, and the delay-insensitive dual-rail code was used for data encoding. Among several weak-indication array multipliers, a weak-indication array multiplier utilizing a biased weak-indication full adder and the strong-indication 2-input AND function is found to have reduced cycle time and power-cycle time product with respect to RTZ and RTO handshaking for 4x4 and 8x8 multiplications. Further, the 4-phase RTO handshaking is found to be preferable to the 4-phase RTZ handshaking for achieving enhanced optimizations of the design metrics.Comment: arXiv admin note: text overlap with arXiv:1903.0943

Asynchronous Early Output Dual-Bit Full Adders Based on Homogeneous and Heterogeneous Delay-Insensitive Data Encoding

This paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-insensitive data encoding. For homogeneous delay-insensitive data encoding only dual-rail i.e. 1-of-2 code is used, and for heterogeneous delay-insensitive data encoding 1-of-2 and 1-of-4 codes are used. The 4-phase return-to-zero protocol is used for handshaking. To demonstrate the merits of the proposed dual-bit full adder designs, 32-bit ripple carry adders (RCAs) are constructed comprising dual-bit full adders. The proposed dual-bit full adders based 32-bit RCAs incorporating redundant logic feature reduced latency and area compared to their non-redundant counterparts with no accompanying power penalty. In comparison with the weakly indicating 32-bit RCA constructed using homogeneously encoded dual-bit full adders containing redundant logic, the early output 32-bit RCA comprising the proposed homogeneously encoded dual-bit full adders with redundant logic reports corresponding reductions in latency and area by 22.2% and 15.1% with no associated power penalty. On the other hand, the early output 32-bit RCA constructed using the proposed heterogeneously encoded dual-bit full adder which incorporates redundant logic reports respective decreases in latency and area than the weakly indicating 32-bit RCA that consists of heterogeneously encoded dual-bit full adders with redundant logic by 21.5% and 21.3% with nil power overhead. The simulation results obtained are based on a 32/28nm CMOS process technology

Generalized disjunction decomposition for the evolution of programmable logic array structures

Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+ë) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures

Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding

Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry adder (RCA) that utilizes single-bit asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA), and carry select adder (CSLA) designs, which are based on homogeneous or heterogeneous delay-insensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dual-operand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation....Comment: arXiv admin note: text overlap with arXiv:1704.0761

Maximum Effectiveness of Electrostatic Energy Harvesters When Coupled to Interface Circuits

Accepted versio