A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate as previous designs (a few Gb/s), but at much lower power than recently published work. Both low static power and low dynamic power (low energy per bit) is aimed for. A capacitive pre-emphasis transmitter lowers the voltage swing and increases the bandwidth using a simple inverter based transceiver and capacitive coupling to the interconnect. The receiver uses Decision Feedback Equalization with a power-efficient continuous-time feedback filter. A low power latch-type voltage sense amplifier is used. The transceiver, fabricated in a 1.2V 90nm CMOS process, achieves 2Gb/s. It consumes only 0.28pJ/b, which is 7 times lower than earlier work

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

Low-power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator

We present a novel driver circuit enabling electro-optic modulation with high extinction ratio from a co-designed silicon ring modulator. The driver circuit provides an asymmetric differential output at 10Gbps with a voltage swing up to 1.5V(pp) from a single 1.0V supply, maximizing the resonance-wavelength shift of depletion-type ring modulators while avoiding carrier injection. A test chip containing 4 reconfigurable driver circuits was fabricated in 40nm CMOS technology. The measured energy consumption for driving a 100fF capacitive load at 10Gbps was as low as 125fJ/bit and 220fJ/bit at 1V(pp) and 1.5V(pp) respectively. After flip-chip integration with ring modulators on a silicon-photonics chip, the power consumption was measured to be 210fJ/bit and 350fJ/bit respectively

Free spectral range electrical tuning of a high quality on-chip microcavity

Reconfigurable photonic circuits have applications ranging from next-generation computer architectures to quantum networks, coherent radar and optical metamaterials. However, complete reconfigurability is only currently practical on millimetre-scale device footprints. Here, we overcome this barrier by developing an on-chip high quality microcavity with resonances that can be electrically tuned across a full free spectral range (FSR). FSR tuning allows resonance with any source or emitter, or between any number of networked microcavities. We achieve it by integrating nanoelectronic actuation with strong optomechanical interactions that create a highly strain-dependent effective refractive index. This allows low voltages and sub-nanowatt power consumption. We demonstrate a basic reconfigurable photonic network, bringing the microcavity into resonance with an arbitrary mode of a microtoroidal optical cavity across a telecommunications fibre link. Our results have applications beyond photonic circuits, including widely tuneable integrated lasers, reconfigurable optical filters for telecommunications and astronomy, and on-chip sensor networks.Comment: Main text: 7 pages, 3 figures. Supplementary information: 7 pages, 9 figure

Phase-Coherent Dynamics of a Superconducting Flux Qubit with Capacitive-Bias Readout

We present a systematic study of the phase-coherent dynamics of a superconducting three-Josephson-junction flux qubit. The qubit state is detected with the integrated-pulse method, which is a variant of the pulsed switching DC SQUID method. In this scheme the DC SQUID bias current pulse is applied via a capacitor instead of a resistor, giving rise to a narrow band-pass instead of a pure low-pass filter configuration of the electromagnetic environment. Measuring one and the same qubit with both setups allows a direct comparison. With the capacitive method about four times faster switching pulses and an increased visibility are achieved. Furthermore, the deliberate engineering of the electromagnetic environment, which minimizes the noise due to the bias circuit, is facilitated. Right at the degeneracy point the qubit coherence is limited by energy relaxation. We find two main noise contributions. White noise is limiting the energy relaxation and contributing to the dephasing far from the degeneracy point. 1/f-noise is the dominant source of dephasing in the direct vicinity of the optimal point. The influence of 1/f-noise is also supported by non-random beatings in the Ramsey and spin echo decay traces. Numeric simulations of a coupled qubit-oscillator system indicate that these beatings are due to the resonant interaction of the qubit with at least one point-like fluctuator, coupled especially strongly to the qubit.Comment: Minor changes. 21 pages, 15 figure

Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures

With the increased complexity and continual scaling of integrated circuit performance, multi-core chips with dozens, hundreds, even thousands of parallel computing units require high performance interconnects to maximize data throughput and minimize latency and energy consumption. High core counts render bus based interconnects inefficient and lackluster in performance. Networks-on-Chip were introduced to simplify the interconnect design process and maintain a more scalable interconnection architecture. With the continual scaling of feature sizes for smaller and smaller transistors, the global interconnections of planar integrated circuits are consuming higher energy proportional to the rest of the chip power dissipation as well as increasing communication delays. Three-dimensional integrated circuits were introduced to shorten global wire lengths and increase chip connectivity. These 3D ICs bring heat dissipation challenges as the power density increases drastically for each additional chip layer. One of the most popularly researched vertical interconnection technologies is through-silicon vias (TSVs). TSVs require additional manufacturing steps to build but generally have low energy dissipation and good performance. Alternative wireless technologies such as capacitive or inductive coupling do not require additional manufacturing steps and also provide the option of having a liquid cooling layer between planar chips. They are typically much slower and consume more energy than their wired counterparts, however. This work compares the interconnection technologies across several different NoC architectures including a proposed sparse 3D mesh for inductive coupling that increases vertical throughput per link and reduces chip area compared to the other wireless architectures and technologies