Out of Context Cache Prefetching

This study examines the efficacy of modifying a hardware cache prefetcher to track and predict context switches and prefetch for incoming processes before they are switched in. The study is composed of three major components - quantifying the amount of contextswitches that can be correctly predicted, examining out of context prefetching on CPU-bound processes and I/O-bound processes, and examining the effects of varying how early before a context switch to begin prefetching.Data suggests that highly accurate context switch prediction is viable, with our own simple prediction unit correctly predicting over 75% of context switches. The study shows that out of context prefetching may not work well with CPU-bound processes, as the positive effects are masked by therelatively long timeslice lengths. Finally, performing out of context prefetching on I/O-bound processes exhibits significant performance improvements over traditional cache prefetching.School of Electrical & Computer Engineerin

Chip Multithreading Systems Need a New Operating System Scheduler

The unpredictable nature of modern workloads, characterized by frequent branches and control transfers, can result in processor pipeline utilization as low as 19%. Chip multithreading (CMT), a processor architecture combining chip multiprocessing and hardware multithreading, is designed to address this issue. Hardware vendors plan to ship CMT systems within the next two years; understanding how such systems will perform is crucial if we are to use them to full advantage. Our simulation experiments show that a CMT-savvy operating system scheduler could improve application performance by a factor of two. In this paper we describe our initial analysis of application performance on CMT systems and propose a design for a scheduler tailored for the needs of a CMT system. 1

Task Activity Vectors: A Novel Metric for Temperature-Aware and Energy-Efficient Scheduling

This thesis introduces the abstraction of the task activity vector to characterize applications by the processor resources they utilize. Based on activity vectors, the thesis introduces scheduling policies for improving the temperature distribution on the processor chip and for increasing energy efficiency by reducing the contention for shared resources of multicore and multithreaded processors