3 research outputs found

    Chip level simulation of the downlink in UTRA-FDD

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    The specifications of UMTS Terrestrial Radio Access (UTRA) for the physical layer of the downlink make use of orthogonal variable spreading factor (OVSF) codes to preserve the orthogonality between downlink channels of different rates and spreading factors. This technique minimises the downlink intra-cell interference. In order to control the inter-cell interference, every base station multiplies the global downlink signal with a cell specific Gold code (scrambling code). Then, while the inter-cell interference may be modelled using the Gaussian hypothesis (that is: replacing the real interference with a Gaussian noise of the same power), the intra-cell interference requires detailed chip level simulations. In this paper we present results of a chip level simulation of the downlink UTRA physical layer. The objective is to evaluate the raw (uncoded) mean bit error rate (BER) of the system in a realistic environment and conditions. Then, by knowing the BER requirements of the different services, one can easily obtain the maximum capacity in terms of simultaneous connections at any combination of bit rates.Peer ReviewedPostprint (published version

    Chip level simulation of the downlink in UTRA-FDD

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    Chip level simulation of the downlink in UTRA-FDD

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    The specifications of UMTS Terrestrial Radio Access (UTRA) for the physical layer of the downlink make use of orthogonal variable spreading factor (OVSF) codes to preserve the orthogonality between downlink channels of different rates and spreading factors. This technique minimises the downlink intra-cell interference. In order to control the inter-cell interference, every base station multiplies the global downlink signal with a cell specific Gold code (scrambling code). Then, while the inter-cell interference may be modelled using the Gaussian hypothesis (that is: replacing the real interference with a Gaussian noise of the same power), the intra-cell interference requires detailed chip level simulations. In this paper we present results of a chip level simulation of the downlink UTRA physical layer. The objective is to evaluate the raw (uncoded) mean bit error rate (BER) of the system in a realistic environment and conditions. Then, by knowing the BER requirements of the different services, one can easily obtain the maximum capacity in terms of simultaneous connections at any combination of bit rates.Peer Reviewe
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