Closed Form Expressions for Delay to Ramp Inputs for On-Chip VLSI RC Interconnect

In high speed digital integrated circuits, interconnects delay can be significant and should be included for accurate analysis. Delay analysis for interconnect has been done widely by using moments of the impulse response, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delay can be estimated accurately at an early physical design stage. For RC trees it is demonstrated that the inverse gamma function provides a provably stable approximation. We used the PERI [13] (Probability distribution function Extension for Ramp Inputs) technique that extends delay metrics for ramp inputs to the more general and realistic non-step inputs. The accuracy of our model is justified with the results compared with that of SPICE simulations. Keywords¾ Moment Matching, On-Chip Interconnect, Probability Distribution function, Cumulative Distribution function, Delay calculation, Slew Calculation, Beta Distribution, VLSI

Piecewise linear delay modeling of digital VLSI circuits

Scope and Method of Study: One of the most important performance measures of digital logic circuits is the delays of switching signals propagating through the logic gates of the circuit. Circuit simulators such as SPICE can find the delay by solving for the current and voltage waveforms as functions of time. Although SPICE can handle the complex, nonlinear behavior of the transistors, it takes a significant amount of computations. Usually no more than a few thousand transistors may be simulated in a reasonable amount of computation time. Simulator such as IRSIM uses the switch model to find the delay, which greatly improves the simulation speed and can process hundreds of thousands of transistors in a reasonable amount of time. But IRSIM predicts delays much less accurate than SPICE because of its delay model inaccuracies. In this paper, a piecewise linear delay model which can evaluate the propagation delay of a CMOS VLSI circuitry with a wide range of input slope is presented. The model also takes into account the influences of short circuit current and dynamic channel charges. By using simple piecewise linear current model and piecewise linear channel charge storage model, it is possible to simulate the modern digital logic circuits in a reasonable amount of time. This model is applicable not only to propagation delay calculation of simple gates but also to that of any general circuit topology.Findings and Conclusions: Excellent agreements with SPICE simulation have been observed in a CMOS inverter, a two-input NAND gate, and an OAI gate cases. The piecewise linear model is capable of predicting the output waveforms and the propagation delay over a variety of input and output conditions. The piecewise linear model can handle large complicated circuits by introducing smaller resistance connected regions. The model is also scalable from one technology to another by choosing different set of technology related model parameters. In general, it is possible to implement a fast circuit simulator based on the piecewise linear model or include the piecewise linear model into an existing circuit simulator such as IRSIM because of its accuracy and speed advantages