New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA

Dynamic symbol size modulation is a type modulation which could provide a fast transmission speed by removing the redundant symbol as compare to fixed symbol size modulation. The dynamic nature of the symbol created an additional problem in hardware design as the size of symbol needed to be defined clearly and it cannot be change and altered once the design has been generated. Thus, to address the issue, this research investigated the best implementation method and performance study of fixed and dynamic symbol size digital baseband modulation for optical communication system in FPGA hardware design. KCU105 FPGA development board and Vivado software were chosen as the main platform to implement the design. A new architecture to implement dynamic symbol size baseband modulation in FPGA is presented in this thesis. Clock control (CC) is used as the research’s based design to create two new architectures which use multiple parallel in serial out (M-PISO) and dynamic parallel in serial out (D-PISO). Next, by using D-PISO architecture, dynamic symbol size modulation namely 8-reverse dual header pulse interval modulation (8-RDHPIM), 8-digital pulse interval modulation (8-DPIM) and fixed symbol size modulation 8-pulse position modulation (8-PPM) were fully implemented in the FPGA which has a transmitter and receiver module. An experimental comparative study was then carried out for each modulation technique. The main parameters investigated were data timing analysis, hardware utilization, power utilization as well as bit error rate performance. From the results, it can be concluded that for power limited system, 8-PPM could be selected as it can maintain a small number of symbol error rate (SER) even during low power transmission which is around -6 dBm. On the other hand, the 8-DPIM and 8-RDHPIM that achieved the transmission speed of 33.3 Mbps and 27.27 Mbps are suitable for systems that require high data speed and minimal clock synchronization

Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs

The reconfigurable computing community has yet to be successful in allowing programmers to access FPGAs through traditional software development flows. Existing barriers that prevent programmers from using FPGAs include: 1) knowledge of hardware programming models, 2) the need to work within the vendor specific CAD tools and hardware synthesis. This thesis presents a series of published papers that explore different aspects of a new approach being developed to remove the barriers and enable programmers to compile accelerators on next generation reconfigurable manycore architectures. The approach is entitled Just In Time Assembly (JITA) of hardware accelerators. The approach has been defined to allow hardware accelerators to be built and run through software compilation and run time interpretation outside of CAD tools and without requiring each new accelerator to be synthesized. The approach advocates the use of libraries of pre-synthesized components that can be referenced through symbolic links in a similar fashion to dynamically linked software libraries. Synthesis still must occur but is moved out of the application programmers software flow and into the initial coding process that occurs when programming patterns that define a Domain Specific Language (DSL) are first coded. Programmers see no difference between creating software or hardware functionality when using the DSL. A new run time interpreter is introduced to assemble the individual pre-synthesized hardware accelerators that comprise the accelerator functionality within a configurable tile array of partially reconfigurable slots at run time. Quantitative results are presented that compares utilization, performance, and productivity of the approach to what would be achieved by full custom accelerators created through traditional CAD flows using hardware programming models and passing through synthesis