Channel Characterization for Chip-scale Wireless Communications within Computing Packages

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018); Torino, Italy; October 201

Channel characterization for chip-scale wireless communications within computing packages

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Peer ReviewedPostprint (author's final draft

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding on the wireless intra-chip channel. This paper first demonstrates that such assumptions do not hold in the context of commercial chips by evaluating losses and dispersion in them. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce the path loss and delay spread of a simulated commercial chip by 47 dB and 7.3x, respectively, enabling intra-chip wireless communications over 10 Gb/s and only 3.1 dB away from the dispersion-free case.Comment: 12 pages, 10 figures. IEEE Transactions on Communications Journal, 202

Exploiting mm-wave communications to boost the performance of industrial wireless networks

This work explores the potentiality of millimeter waves (mmW) as physical layer in industrial wireless networks. Innovative models and a link design method are proposed to achieve reliable communication, at a distance of tens of meters for a single hop, even in harsh environments. By exploiting the worldwide-free band of several GHz, available around 60 GHz, mmW links allow to achieve a performance boosting of up to two orders of magnitude, w.r.t. conventional sub-6-GHz wireless links, in indoor industrial environments. Time slotted channel hopping and frequency-diversity can be implemented with a large number of channels, and with high bit rate (several Mb/s per channel). This allows for robust networking of high data-rate sensors, such as cameras, radars, or laser scanners. Featuring a low bit error rate, mmW communication allows for low-latency link and large number of hops in networks with a large radius. Finally, it ensures interference separation from operating frequencies of electrical machines, switching converters, and other industrial wireless networks (e.g., 802.11 or 802.15). Implementation results for key HWblocks in low-cost technologies show the feasibility of mmW communication nodes with low-power and compact size

Engineer the channel and adapt to it: enabling wireless intra-chip communication

© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The authors gratefully acknowledge support from the Spanish MINECO under grant PCIN-2015-012, from the EU’s H2020 FET-OPEN program under grants No. 736876 and No. 863337, and by the Catalan Institution for Research and Advanced Studies (ICREA).Peer ReviewedPostprint (author's final draft

Exploration of intercell wireless millimeter-wave communication in the landscape of intelligent metasurfaces

Software-defined metasurfaces are electromagnetically ultra-thin, artificial components thatcan provide engineered and externally controllable functionalities. The control over these functionalities isenabled by the metasurface tunability, which is implemented by embedded electronic circuits that modifylocally the surface resistance and reactance. Integrating controllers within the metasurface able them tointercommunicate and adaptively reconfigure, thus imparting a desired electromagnetic operation, opens thepath towards the creation of an artificially intelligent (AI) fabric where each unit cell can have its own sensing,programmable computing, and actuation facilities. In this work we take a crucial step towards bringing theAI metasurface technology to emerging applications, in particular exploring the wireless mm-wave intercellcommunication capabilities in a software-defined HyperSurface designed for operation in the microwaveregime. We examine three different wireless communication channels within the landscape of the reflectivemetasurface: Firstly, in the layer where the control electronics of the HyperSurface lie, secondly inside adedicated layer enclosed between two metallic plates, and, thirdly, inside the metasurface itself. For each casewe examine the physical implementation of the mm-wave transceiver nodes, we quantify communicationchannel metrics, and we identify complexity vs. performance trade-offs.Peer ReviewedPostprint (published version

Millimeter-wave interconnects for intra- and inter-chip transmission and beam steering in NoC-based multi-chip systems

The primary objective of this work is to investigate the communication capabilities of short-range millimeter-wave (mm-wave) communication among Network-on-Chip (NoC) based multi-core processors integrated on a substrate board. To address the demand for high-performance multi-chip computing systems, the present work studies the transmission coefficients between the on-chip antennas system for both intra- and inter-chip communication. It addresses techniques for enhancing transmission by using antenna arrays for beamforming. It also explores new and creative solutions to minimize the adverse effects of silicon on electromagnetic wave propagation using artificial magnetic conductors (AMC). The following summarizes the work performed and future work. Intra- and inter-chip transmission between wireless interconnects implemented as antennas on-chip (AoC), in a wire-bonded chip package are studied 30GHz and 60 GHz. The simulations are performed in ANSYS HFSS, which is based on the finite element method (FEM), to study the transmission and to analyze the electric field distribution. Simulation results have been validated with fabricated antennas at 30 GHz arranged in different orientations on silicon dies that can communicate with inter-chip transmission coefficients ranging from -45dB to -60dB while sustaining bandwidths up to 7GHz. The fabricated antennas show a shift in the resonant frequency to 25GHz. This shift is attributed to the Ground-Signal-Ground (GSG) probes used for measurement and to the Short-Open-Load (SOLT) calibration which has anomalies at millimeter-wave frequencies. Using measurements, a large-scale log-normal channel model is derived which can be used for system-level architecture design. Further, at 60 GHz densely packed multilayer copper wires in NoCs have been modeled to study their impact on the wireless transmission between antennas for both intra- and inter-chip links and are shown to be equivalent to copper sheets. It is seen that the antenna radiation efficiency reduces in the presence of these densely packed wires placed close to the antenna elements. Using this model, the reduction of inter-chip transmission is seen to be about 20dB as compared to a system with no wires. Lastly, the transmission characteristics of the antennas resonating at 60GHz in a flip-chip packaging environment are also presented