Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test pattern generation (ATPG) approaches, which target faults only at the boundaries of library cells. The CAT methodology consists of two stages. Stage 1, based on dedicated analog simulation, library characterization per cell identifies which cell-level test pattern detects which cell-internal defect; this detection information is encoded in a defect detection matrix (DDM). In Stage 2, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells. This paper focuses on Stage 1, library characterization, as both test quality and cost are determined by the set of cell-internal defects identified and simulated in the CAT tool flow. With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to as full set, of potential open- and short-defect locations based on cell layout. However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage 1 unaffordable. Subsequently, to reduce the simulation time, we collapse the full set to a compact set of defects which serves as input of the defect simulation. The full set is stored for the diagnosis and failure analysis. With inspecting the simulation results, we propose a method to verify the test quality based on the compact set of defects and, if necessary, to compensate the test quality to the same level as that based on the full set of defects. For 351 combinational library cells in Cadence’s GPDK045 45nm library, we simulate only 5.4% defects from the full set to achieve the same test quality based on the full set of defects. In total, the simulation time, via linear extrapolation per cell, would be reduced by 96.4% compared with the time based on the full set of defects

Recent Trends and Perspectives on Defect-Oriented Testing

Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips utilized in mission-critical applications. The research community and industry have been investigating new test approaches such as device-aware test, cell-aware test, path-delay test, and even test methodologies based on the analysis of manufacturing data to move the scope from OPPM to OPPB. This special session presents four contributions, from academic researchers and industry professionals, to enable better chip quality. We present results on various activities towards this objective, including device-aware test, software-based self-test, and memory test

A fully digital power supply noise thermometer

Power Supply Noise (PSN) is one of the main concerns in scaled technology circuits, both if performance reliability must be assured and if power supply is to be dynamically reduced for dissipation regulation. In this paper we propose a new system for digitally sensing Power Supply and Ground levels that can be both transferred to the output for verification purposes and used by a control block within the circuit under test (CUT) for the activation of power aware policies. The sensor system shows very low overhead in terms of power and area, and works at the nominal CUT frequency. It allows to change on-site the Power Supply and Ground ranges to be sensed and, after a fine tuning, can be arranged for a process variation aware measures. This sensor is fully digital and standard cell based and can be used for every type of architecture on a systematic basis for PSN measure as scan chains are for fault verification. It thus represents a change of paradigm in the way in which PSN measure systems are thought nowaday

STAHL: A Novel Scan-Test-Aware Hardened Latch Design

As modern technology nodes become more susceptible to soft errors, many radiation hardened latch designs have been proposed. However, redundant circuitry used to tolerate soft errors in such hardened latches also reduces the test coverage of cell-internal manufacturing defects. To avoid potential test escapes that lead to soft error vulnerability and reliability issues, this paper proposes a novel Scan-Test-Aware Hardened Latch (STAHL). Simulation results show that STAHL has superior defect coverage compared to previous hardened latches while maintaining full radiation hardening in function mode.24th IEEE European Test Symposium (ETS\u2719), May 27-31, 2019, Baden-Baden, German

Towards an Efficient Context-Aware System: Problems and Suggestions to Reduce Energy Consumption in Mobile Devices

Looking for optimizing the battery consumption is an open issue, and we think it is feasible if we analyze the battery consumption behavior of a typical context-aware application to reduce context-aware operations at runtime. This analysis is based on different context sensors configurations. Actually existing context-aware approaches are mainly based on collecting and sending context data to external components, without taking into account how expensive are these operations in terms of energy consumption. As a first result of our work in progress, we are proposing a way for reducing the context data publishing. We have designed a testing battery consumption architecture supported by Nokia Energy Profiler tool to verify consumption in different scenarios

Acceptance of non-invasive prenatal testing by cell free foetal DNA for foetal aneuploidy in a developing country: experience at a tertiary care centre in India

Background: Non-invasive prenatal testing is a new technique which is deepening its root all over the world. Its tremendous potential lies in its ability of using cell free fetal DNA from the plasma of pregnant women. However, to what extent the technology has reached to a common person is also to be given a thought. hence the study was planned to assess the acceptability of non-invasive prenatal testing in Indian settings, to study about the awareness and baseline knowledge about Down’s syndrome, to study the correlation between various indications of prenatal testing for aneuploidy and results of noninvasive prenatal testing.Methods: Noninvasive cell free fetal NA testing for aneuploidy was an informed patient choice after pre-test counseling. Patients with a positive test result were offered invasive prenatal diagnosis for confirmation of test results.Results: The diagnostic potential of cell free DNA for fetal aneuploidy matched equally with invasive tests avoiding slight but yet considerable risk of invasive tests. However, we found that, 90 % of patients in a tertiary centre hospital in India were not aware of trisomy 21 and various options available for prenatal screening for aneuploidy.Conclusions: Newer genomic technology involving cell free maternal DNA is a new storm in prenatal diagnosis. Its application in clinical practice is the need of the hour, however, the lack of awareness, high cost and unavailability of the test in the country appears to be a major limiting factor for its poor acceptability