A Four-stage Power and Area Efficient OTA with 30 × (400pf – 12nf) Capacitive Load Drive Range

Multistage operational transconductance amplifier (OTA) has been a major research focus as a solution to high DC Gain high Gain Bandwidth and wide voltage swing requirement on sub-micron devices. These system requirements, in addition to ultra-large capacitive load drivability (nF-range load capacitor), are useful in applications including LCD drivers, low dropout (LDO) linear regulators, headphone drivers, etc. The major drawback of multistage OTAs is the stability concerns since each added stage introduces low frequency poles. Numerous compensation schemes for three stage OTAs have been proposed in the past decade with only a few four stage OTA in literature. The proposed design is a four stage OTA which uses an active zero block (AZB) to provide left half plane (LHP) zero to help with phase degradation. AZB is embedded in the second stage ensuring reuse of existing block hence providing area and power savings. This design also uses single miller capacitor in the outer loop which ensures improved speed performance with minimal area overhead. A very reliable slew helper is implemented in this design to help with the large signal performance. The slew helper is only operational in the events slewing and does not affect the small signal performance. The proposed design achieves a DC gain of 114 dB, GBW > 1.77MHz and PM > 46.9⁰ for capacitive load ranging from 400pF–12nF (30x) which is the highest recorded range in literature for these type of compensation. It does this by consuming a total power of 143.5µW and an area of 0.007mm^2

Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling

Out-of-Loop Compensation Method for Op-Amps Driving Heavy Capacitive Loads

It is well known that real op-amps do not share most of the desirable characteristics of an ideal one, particularly those of gain and output impedance. When presented with a capacitive load, such as a MOSFET or ADC, feedback in an op-amp circuit can quickly become unstable. This thesis studies and characterizes an op-amp’s output impedance and how its interaction with this type of load creates a parasitic pole which leads to instability. Applying ideas from feedback control theory, a model for studying the problem is developed from which a generalized method for compensating the undesirable circumstance is formulated. Even in a zero-input state, many real op-amps driving capacitive loads can experience unforced oscillations. A case study is performed with three commonly used devices. First, the output impedance is determined by its dependence on the unity-gain bandwidth, load capacitance, and oscillation frequency. It is fitted into a second-order feedback control model that allows for an analytical study of the problem. It is then shown that a carefully designed passive network can be introduced between the load and op-amp to obtain a properly damped system free of oscillation and well-behaved. Using a shunt resistor is a known and commonly used method for lowering an op-amp’s output impedance to gain stability. This work considers the converse addition of a series capacitor to instead lower the load capacitance seen by the op-amp, a seemingly complementary method that achieves the same goal. A generalized, composite compensation method is developed that uses both the shunt resistor and series capacitor– a strategy not yet found in literature. Relevant formulas for damping ratio and natural frequency are derived that allow the design of a passive compensation network. Furthermore, tradeoffs between compensation, voltage swing, current consumption, and power usage are considered. An emphasis is placed on comparing simulated versus real circuits to highlight the fact that any problem is much worse in real-life than in a simulation. SPICE models and programs aim to de-idealize certain device characteristics, but often cannot account for environmental conditions and manufacturing variance. Thus, an importance is placed on experimental verification guided by simulations

Circuits and algorithms for pipelined ADCs in scaled CMOS technologies

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.MIT Barker Engineering Library copy: printed in pages.Also issued printed in pages.Includes bibliographical references (leaves 179-184).CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally used in switched capacitor circuits. This research involves two complementary methods for addressing scaling issues. First is the development of two blind digital calibration techniques. Decision Boundary Gap Estimation (DBGE) removes static non-linearities and Chopper Offset Estimation (COE) nulls offsets in pipelined ADCs. Second is the development of circuits for a new architecture called zero-crossing based circuits (ZCBC) that is more amenable to scaling trends. To demonstrate these circuits and algorithms, two different ADCs were designed: an 8 bit, 200MS/s in TSMC 180nm technology, and a 12 bit, 50 MS/s in IBM 90nm technology. Together these techniques can be enabling technologies for both pipelined ADCs and general mixed signal design in deep sub-micron technologies.by Lane Gearle Brooks.Ph.D