Diffusive Transport in Quasi-2D and Quasi-1D Electron Systems

Quantum-confined semiconductor structures are the cornerstone of modern-day electronics. Spatial confinement in these structures leads to formation of discrete low-dimensional subbands. At room temperature, carriers transfer among different states due to efficient scattering with phonons, charged impurities, surface roughness and other electrons, so transport is scattering-limited (diffusive) and well described by the Boltzmann transport equation. In this review, we present the theoretical framework used for the description and simulation of diffusive electron transport in quasi-two-dimensional and quasi-one-dimensional semiconductor structures. Transport in silicon MOSFETs and nanowires is presented in detail.Comment: Review article, to appear in Journal of Computational and Theoretical Nanoscienc

Electron mobility in surface- and buried- channel flatband In_0.53Ga_0.47As MOSFETs with ALD Al₂O₃ gate dielectric.

In this paper, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried In<sub>0.53</sub>Ga<sub>0.47</sub>As channel devices employing an Atomic Layer Deposited (ALD) Al<sub>2</sub>O<sub>3</sub> gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm<sup>2</sup>/V·s and 6600 cm<sup>2</sup>/V·s at a carrier density of 3×1012 cm<sup>-2</sup> for the surface and buried channel structures respectively were determined. In contrast to similarly scaled inversion-channel devices, we find that mobility in surface channel flatband structures does not drop rapidly with electron density, but rather high mobility is maintained up to carrier concentrations around 4x10<sup>12</sup> cm<sup>-2</sup> before slowly dropping to around 2000 cm<sup>2</sup>/V·s at 1x10M<sup>13</sup> cm<sup>-2</sup>. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for future low power, highly scaled CM

The effect of low-energy ion-implantation on the electrical transport properties of Si-SiO2 MOSFETs

Using silicon MOSFETs with thin (5nm) thermally grown SiO2 gate dielectrics, we characterize the density of electrically active traps at low-temperature after 16keV phosphorus ion-implantation through the oxide. We find that, after rapid thermal annealing at 1000oC for 5 seconds, each implanted P ion contributes an additional 0.08 plus/minus 0.03 electrically active traps, whilst no increase in the number of traps is seen for comparable silicon implants. This result shows that the additional traps are ionized P donors, and not damage due to the implantation process. We also find, using the room temperature threshold voltage shift, that the electrical activation of donors at an implant density of 2x10^12 cm^-2 is ~100%.Comment: 11 pages, 10 figure

Design space for low sensitivity to size variations in [110] PMOS nanowire devices: The implications of anisotropy in the quantization mass

A 20-band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to examine the ON-current variations to size variations of [110] oriented PMOS nanowire devices. Infinitely long, uniform, rectangular nanowires of side dimensions from 3nm to 12nm are examined and significantly different behavior in width vs. height variations are identified and explained. Design regions are identified, which show minor ON-current variations to significant width variations that might occur due to lack of line width control. Regions which show large ON-current variations to small height variations are also identified. The considerations of the full band model here show that ON-current doubling can be observed in the ON-state at the onset of volume inversion to surface inversion transport caused by structural side size variations. Strain engineering can smooth out or tune such sensitivities to size variations. The cause of variations described is the structural quantization behavior of the nanowires, which provide an additional variation mechanism to any other ON-current variations such as surface roughness, phonon scattering etc.Comment: 24 pages, 5 figure

Bandstructure Effects in Ultra-Thin-Body DGFET: A Fullband Analysis

This paper discusses a few unique effects of ultra-thin-body double-gate NMOSFET that are arising from the bandstructure of the thin film Si channel. The bandstructure has been calculated using 10-orbital $sp^3d^5s^*$ tight-binding method. A number of intrinsic properties including band gap, density of states, intrinsic carrier concentration and parabolic effective mass have been derived from the calculated bandstructure. The spatial distributions of intrinsic carrier concentration and $$ effective mass, arising from the wavefunction of different contributing subbands are analyzed. A self-consistent solution of Poisson-Schrodinger coupled equation is obtained taking the full bandstructure into account, which is then applied to an insightful analysis of volume inversion. The spatial distribution of carriers over the channel of a DGFET has been calculated and its effects on effective mass and channel capacitance are discussed.Comment: 13 pages, 21 figure

Electron Mobility and Magneto Transport Study of Ultra-Thin Channel Double-Gate Si MOSFETs

We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range 7-17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9 m2/Vs, which was measured from a 16.5 nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing