Design of a 3 GHz fine resolution LC DCO

In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin

Digital controlled oscillator (DCO) for all digital phase-locked loop (ADPLL) – a review

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL

Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning

A digitally controlled oscillator (DCO) that achieves a minimum frequency quantization step of 150 Hz without any dithering is presented. The fine digital tuning is obtained through a capacitive degeneration of a portion of the transistor switching pair used in a classical LC-tank oscillator. The new tuning circuitry does not appreciably affect the intrinsic oscillator phase noise and allows to trim the frequency with a programmable resolution for calibration and multi-standard operation. A prototype integrated in 65 nm CMOS technology exhibits a phase noise of @ 1 MHz drawing 16 mA from a supply of 1.8 V, resulting in a FoM of 183 dBc/Hz. The active area is 700 450

Digitally Controlled Oscillator for mm-Wave Frequencies

In the fifth generation of mobile communication, 5G, frequencies above 30 GHz, so-called millimeter-wave (mm-wave) frequencies are expected to play a prominent role. For the synthesis of these frequencies, the all-digital phase locked loop (ADPLL) has recently gained much attention. A core component of the ADPLL is the digitally controlled oscillator (DCO), an oscillator that tunes the frequency discretely. For good performance, the frequency steps must be made very small, while the total tuning range must be large. This thesis covers several coarse- and fine-tuning techniques for DCOs operating at mm-wave frequencies. Three previously not published fine-tuning schemes are presented: The first one tunes the second harmonic, which will, due to the Groszkowski effect, tune the fundamental tone. The second one is a current-modulation scheme, which utilizes the weak current-dependence of the capacitance of a transistor to tune the frequency. In the third one, a digital-to-analog converter (DAC) is connected to the bulk of the differential pair and tunes the frequency by setting the bulk voltage. The advantages and disadvantages of the presented tuning schemes are discussed and compared with previously reported fine-tuning schemes. Two oscillators were implemented at 86 GHz. Both oscillator use the same oscillator core and hence have the same power consumption and tuning range, 14.1 mW and 13.9%. A phase noise of -89.7 dBc/Hz and -111.4 dBc/Hz at 1 MHz and 10 MHz offset, respectively, were achieved, corresponding to a Figure-of-Merit of -178.5 dBc/Hz. The first oscillator is fine-tuned using a combination of a transformer-based fine-tuning and the current modulation scheme presented here. The achieved frequency resolution is 55 kHz, but can easily be made finer. The second oscillator utilizes the bulk bias technique to achieve its fine tuning. The fine-tuning resolution is here dependent on the resolution of the DAC; a 100μV resolution corresponds to a resolution of 50 kHz.n 2011, the global monthly mobile data usage was 0.5 exabytes, or 500 million gigabytes. In 2016, this number had increased to 7 exabytes, an increase by a factor 14 in just five years, and there are no signs of this trend slowing down. To meet the demands of the ever increasing data usage, engineers have begun to investigate the possibility to use significantly higher frequencies, 30 GHz or higher, for mobile communication than what is used today, which is 3 GHz or below. To be able to transmit and receive data at these high frequency, an oscillator capable of operating at these frequencies are required. An oscillator is an electrical circuit that generates an alternating current (a current that first goes one way, and then the other) at a specific frequency. Below is an example to illustrate to function and importance of the oscillator: Imagine driving a car and listening to the radio. Suddenly, a horrendous song starts playing from the radio, so you instantly tune to another station and find some great, smooth jazz. Satisfied, you lean back and drive on. But what exactly happened when you "tuned to another station"? What you really did was changing the frequency of the oscillator, which can be found in the radio receiver of the car. The radio receiver filters out all frequencies, except for the frequency of the local oscillator. So by setting the frequency of the local oscillator to the frequency of the desired radio channel, only this radio channel will reach the speakers of the car. Thus, the oscillator must be able to vary its frequency to any frequency that a radio station can transmit on. While an old car radio may seem like a simple example, the very same principle is used in mobile communication, even at frequencies above 30 GHz. The oscillator is also used in the same way when transmitting signals, so that the signals are transmitted on the correct frequency. The design of the local oscillator is a hot topic among radio engineers. A poorly designed oscillator will ruin the performance of the whole receiver or transmitter. This thesis covers the design of a special type of oscillators, called digital controlled oscillators or DCO, operating at 30 GHz or higher. The frequency of these oscillators are determined by a digital word (ones and zeros), instead of using an analog voltage, which is traditionally used. Digital control results in greater flexibility and higher noise-resilience, but it also means that the frequency can’t be changed continuously, but rather in discrete steps. This discrete behavior will cause noise in the receiver. To minimize this noise, the frequency steps should be minimized. In this thesis, we have proposed a DCO design, operating at 85.5 GHz, which can be tuned almost 7 % in either direction. To our knowledge, no other DCO operates at such high frequencies. In the proposed oscillators the frequency steps are only 55 kHz apart, which is so small that its effect on the radio receiver can, with a good conscience, be ignored. This is achieved with a novel technique that makes tiny, tiny changes in the current that passes through the oscillator

Design and investigation of nanometric and submicron integrated circuits for voltage and digital controlled oscillators

Disertacijoje nagrinėjama LC-ĮVG ir LC-SVG, architektūros, modeliai bei jų kūrimas taikant nanometrines ir submikronines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad tinkamos architektūros parinkimas ir integrinių grandynų technologijų taikymas įgalina sukurti reikiamų parametrų ir kokybės 2–10 GHz įtampa ir skaitmeniniu būdu valdomus generatorius nanometriniuose ir submikroniniuose integriniuose grandynuose. Darbo tikslas – sukurti 2–10 GHz LC-ĮVG ir LC-SVG blokus nanometrinėse bei submikroninėse KMOP integrinių grandynų technologijose, leidžiančius pasiekti reikiamus parametrus skirtus daugiastandarčiams daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams iki 10 GHz. Darbe išspręsti tokie uždaviniai: ištirtos LC-ĮVG ir LC-SVG architektūros skirtingose integrinių grandynų KMOP technologijose ir parinkta optimali architektūra integrinių grandynų sukūrimui, pasiūlytos naujos kokybės funkcijos skirtos LC-ĮVG ir LC-SVG palyginamajai analizei, sukurti ir ištirti LC-ĮVG ir LC-SVG integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatūros ir autoriaus publikacijų disertacijos tema sąrašai ir trys priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašomas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma tyrimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, ginamieji teiginiai. Įvado pabaigoje pristatomos disertacijos tema autoriaus paskelbtos publikacijos ir pranešimai konferencijose bei disertacijos struktūra. Pirmajame skyriuje analizuojamos dažnio generatorių architektūros, jų pritaikymas bei jų pagrindiniai parametrai. Pateikiami pagrindiniai dažnio generatorių parametrai. Apžvelgiamos kokybės funkcijos, nusakančios dažnio generatorių pagrindinius parametrus skirtus palyginamajai analizei. Antrajame skyriuje pateikiamos naujos FOMTT FOMT2 kokybės funkcijos, kuriomis remiantis vertinami valdomo dažnio generatorių pagrindiniai parametrai palyginamajai analizei. Taip pat pateikiami induktyvumo ritės kokybės gerinimo būdai. Trečiajame skyriuje, taikant kompiuterinių skaičiavimų ir eksperimentinius metodus yra kuriami ir tiriami įtampa ir skaitmeniniu būdu valdomų generatorių bei papildomų blokų integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 2 – mokslo žurnaluose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 3 – tarptautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analy-tics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duomenų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti dvylikoje mokslinių konferencijų Lietuvoje ir užsienyje.Disertacij