A Novel Fully Differential Second Generation Current Conveyor and Its Application as a Very High CMRR Instrumentation Amplifier

This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW.  Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits

An electrocardiogram readout circuit based on CMOS operational floating current conveyor

Electrocardiogram (ECG) is used in diagnosing heart diseases. It is designed as integration between current-mode instrumentation amplifiers (CMIA) and low pass filter (LPF). Normal heart behavior can be identified simply by normal ECG that consists of signal while heart disorder can be recognized by having differences in the features of their corresponding ECG waveform. A novel integrated CMOS-based operational floating current conveyor (OFCC) circuit is proposed. OFCC is a five port general purpose analog building block which combines all the features of different current mode devices such as the second generation current conveyor (CCII), the current feedback operational amplifier (CFA), and the operational floating conveyor (OFC). The OFFC is modeled and simulated using UMC 130nm CMOS technology kit in Cadence with a supply voltage 1.2V. The ECG readout circuit has been designed using the proposed OFCC as a building block. The advantages of this: it is integrated, noise factor is small as the proposed OFCC has the lowest input noise voltage and the layout is simple as it is a single block that can be repeated several times

Design of the fully differential operational floating conveyor and its applications

Analog circuits can be generally classified into two broad categories: The first one includes analog circuits operating in the voltage mode, while the second category includes those operating in the current mode. Voltage mode analog circuit’s bandwidth is highly dependent on the gain via the gain bandwidth product (GBP). To solve this problem, many current mode circuits are developed such as the second generation Current Conveyor (CCII) and the Operational Floating Conveyor (OFC). A novel concept of the Fully Differential Operational Floating Conveyor (FD-OFC) is presented for the first time, to the best of the author’s knowledge. A CMOS design for the proposed FD-OFC is introduced as an 8 (4x4) port general purpose analog building block. The FD-OFC design is implemented using two different realizations. The proposed design has the advantage of low power consumption as it operates under biasing conditions of only 1.2 V while its wide bandwidth reaches 600 MHz. These operating conditions recommend the proposed device to be integrated to a wide range of low power-wide high speed applications. The terminal behavior of the proposed device is mathematically modeled and its operation is simulated using the UMC 130 nm technology kit in Cadence environment. Differential voltage amplifier, current mode instrumentation amplifier (CMIA) and Fully Differential second generation Current Conveyor (FDCCII) are examples of the presented applications based on the proposed FD-OFC

Investigation of Current Sensing Using Inherent Resistance

A novel method of current sensing using resistance of power delivery path is introduced as a mean to measure static or dynamic load current in high-power system-on-chips, where conventional methods deemed inadequate. It is named “IRS” here, and it stands for Inherent Resistance Current Sensing. To explain its application and to provide motivation beyond this work, pros and cons of conventional techniques are reviewed with a look at previous works done in this area. It is followed with review of discreet implementation of the sensor (IRS) in chapter three. The measurements results collected using the discrete circuits are included with an in-depth analysis of the results and compensation techniques. It offers insight to effectiveness of the solution and its potential, while highlighting shortcomings and limitation of discrete implementation. This would set the tone to design integrated version of the sensor. In order to select amplifier architecture, a rundown of common methods to construct the instrumentation amplifier is discussed in chapter 4, primarily based on the latest work already done in this field per cited references. This is to help readers to get an overall view of the challenges and techniques to overcome them. Finally, the architecture for the integrated version of the sensor (IRS) is presented, with a proof of concept design. The design is targeted for low voltage VLSI systems to allow integration within large SoCs such as GPUs and CPUs. The primary block, the instrumentation amplifier, is constructed using rail-to-rail current conveyers and simulated using TSMC 32nm process node. The simulation results are analyzed and observations are provided