Broadband Excitation and Active Control of Terahertz Plasmons in Graphene

A novel broadband technique to effectively launch plasmons along a single graphene layer at terahertz (THz) frequencies is proposed. To this end, the coupling of the electromagnetic wave from a readily available plasmonic waveguide established by a periodically corrugated metallic surface to the graphene sheet is proposed. As will be shown, this technique can significantly surmount the need for efficient excitation of plasmons in graphene. For this purpose, an analytical technique based on transmission line theory is employed to calculate the scattering parameters of the connection of the plasmonic waveguides. In this manner, the gating effects of the graphene waveguide on the input reflection and transmission of the junction are also investigated. For comparison, a full wave numerical simulator is employed

Arquiteturas de Pipeline Assíncronas Register Less NULL Convention Logic (RL-NCL) Usando Portas Básicas

Asynchronous circuits is an alternative to design digital systems that is becoming the interest of many researchers in the digital design area mainly due to it’s low-power consumption and robustness. One of the most compelling design paradigms of asynchronous circuits is the NULL Convention Logic (NCL). The pipeline is a very common technique used in digital circuits to achieve high throughput. Although one can implement a pipeline using NCL gates, recent works have shown that register-less pipelines are possible using modified NCL gates. In this paper we propose two new Register-Less NCL (RL-NCL) pipeline architectures and two new methods to design NCL gates, which can be implemented even in Field Programmable Gate Arrays (FPGAs) or using the standard cells method. The new design of the proposed architecture was able to achieve an average area reduction of 27,32%, an average latency reduction of 14,1% and an average throughput increase of 5,54% comparing with the conventional NCL pipeline architecture.Los circuitos asíncronos son una alternativa para el diseño de sistemas digitales que se está convirtiendo en el interés de muchos investigadores en el área del diseño digital debido principalmente a su bajo consumo y robustez. Uno de los paradigmas de diseño más convincentes de los circuitos asíncronos es la NULL Convention Logic (NCL). La pipeline es una técnica muy común utilizada en circuitos digitales para lograr un alto rendimiento. Aunque se puede implementar una pipeline utilizando puertas NCL, trabajos recientes han demostrado que las pipelines sin registro son posibles utilizando puertas NCL modificadas. En este artículo, propusimos dos nuevas arquitecturas de pipeline Register-Less NCL (RL-NCL) y un paradigma de diseño, que pueden implementarse incluso en Field Programmable Gate Arrays (FPGA) o utilizando el método de celdas estándar. El nuevo diseño de la arquitectura propuesta logró una reducción media del área del 27,32%, una reducción media de la latencia del 14,1% y un aumento medio del rendimiento del 5,54% en comparación con la arquitectura de pipeline NCL convencional.Circuitos assíncronos é uma alternativa para projetar sistemas digitais que vem despertando o interesse de muitos pesquisadores na área de projeto digital principalmente devido ao seu baixo consumo de energia e robustez. Um dos paradigmas de projeto mais atraentes de circuitos assíncronos é o NULL Convention Logic (NCL). O pipeline é uma técnica muito comum usada em circuitos digitais para obter alto rendimento. Embora seja possível implementar um pipeline usando portas NCL, trabalhos recentes mostraram que pipelines sem registro são possíveis usando portas NCL modificadas. Neste artigo propomos duas novas arquiteturas de pipeline NCL Register-Less (RL-NCL) e dois novos métodos para projetar portas NCL, que podem ser implementadas até mesmo em Field Programmable Gate Arrays (FPGAs) ou usando o método de células padrão. O novo design da arquitetura proposta foi capaz de alcançar uma redução média de área de 27,32%, uma redução média de latência de 14,1% e um aumento médio de throughput de 5,54% em comparação com a arquitetura de pipeline NCL convencional

Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures

Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL)

Multi-Physics Modeling of Terahertz and Millimeter-Wave Devices

In recent years, there have been substantial efforts to design and fabricate millimeter-wave and terahertz (THz) active and passive devices. Operation of microwave and photonic devices in THz range is limited due to limited maximum allowable electron velocity at semiconductor materials, and large dimensions of optical structures that prohibit their integration into nano-size packages, respectively. In order to address these issues, the application of surface plasmons (SPs) is mostly suggested to advance plasmonic devices and make this area comparable to photonics or electronics. In this research, the feasibility of implementing THz and millimeter-wave plasmonic devices inside different material platforms including: two-dimensional electron gas (2DEG) layers of hetero-structures, silicon wafers and graphene, are elaborated. To this end, an analytical model is developed to describe the propagation of two-dimensional plasmons along electron gas layers of biased hetero-structures. Using this analytical model, the existence of new plasmonic modes along the biased electron gas is reported for the first time. For an independent verification, a novel multi-physics simulator is developed to analyze active terahertz plasmonic structures. It is also anticipated that the solver can offer novel ideas for guiding the SPs inside the future plasmonic circuits. In a different approach to design plasmonic devices in a widely used material platform, silicon, a THz modulator is proposed. Using a full wave simulator, it is shown that plasmonic wave can propagate along an indented n-type doped silicon wafer (which is later covered with a metallic layer) with large attenuations. However, the signal losses can be prohibited by applying bias voltages onto the metal as the thickness of the depletion layer between the metal and silicon increases. At the end, an effective method to couple incident waves onto an infinitely thin graphene mono-layer is presented. As will be illustrated, the surface waves along a corrugated metal can efficiently transit into graphene and successfully launch plasmons

A null convention logic based platform for high speed low energy IP packet forwarding

By 2020, it is predicted that there will be over 5 billion people and 38.5 billion Internet-ofThings devices on the Internet. The data generated by all these users and devices will have to be transported quickly and efficiently. Routers forming the backbone of this Internet already support multiple 100 Gbps ports meaning that they would have to perform upwards of 200 Million destination addresses lookups per second in the packet forwarding block that lies in the router ‘data-path’. At the same time, there is also a huge demand to make the network infrastructure more energy efficient. The work presented in this thesis is motivated by the observation that traditional synchronous digital systems will have increasing difficulty keeping up with these conflicting demands. Further, with reducing device geometries, extremes in “process, voltage and temperature” (PVT) variability will undermine reliable synchronous operation. It is expected that asynchronous design techniques will be able to overcome many of these problems and offer a means of lowering energy while maintaining high throughput and low latency. This thesis investigates existing address lookup algorithms and investigates the possibility of combining various approaches to improve energy efficiency without affecting lookup performance. A quasi delay-insensitive asynchronous methodology - Null Convention Logic (NCL) - is then applied to this combined design. Techniques that take advantage of the characteristics of the design methodology and the lookup algorithm to further improve the area, energy and latency characteristics are also analysed. The IP address lookup scheme utilised here is a recent algorithmic approach that uses compact binary-tries and was selected for its high memory efficiency and throughput. The design is pipelined, and the prefix information is stored in large RAMs. A Boolean synchronous implementation of the algorithm is simulated to provide an initial performance benchmark. It is observed that during the address lookup process nearly 68% of the trie accesses are to nodes that contained no prefix information. Bloom filter structures that use non-cryptographic hashes and single-bit memory are introduced into the address lookup process to prevent these unnecessary accesses, thereby reducing the energy consumption. Three non-cryptographic hashing algorithms (CRC32, Jenkins and Murmur) are also analysed for their suitability in Bloom filters, and the CRC32 is found to offer the most suitable trade-off between complexity and performance. As a first step to applying the NCL design methodology, NCL implementations of the hashing algorithms are created and evaluated. A significant finding from these experiments is that, unlike Boolean systems, latency and throughput in NCL systems are only loosely coupled. An example Jenkins hash implementation with eight pipeline stages and a cycle time of 3.2 ns exhibits a total latency of 6 ns, whereas an equivalent synchronous implementation with a similar clock period exhibits a latency of 25.6 ns. Further investigations reveal that completion detection circuits within the NCL pipelines impair throughput significantly. Two enhancements to the NCL circuit library aimed particularly at optimising NCL completion detection are proposed and analysed. These are shown to enable completion detection circuits to be built with the same delay but with 30% smaller area and about 75% lower peak current compared to the conventional approach using gates from the standard NCL library. An NCL SRAM structure is also proposed to augment the conventional 6-T cell array with circuits to generate the handshaking signals for managing the NCL data flow. Additionally, a dedicated column of cells called the Null-storage column is added, which indicates if a particular address in the RAM stores no Data, i.e., it is in its Null state. This additional hardware imposes a small area overhead of about 10% but allows accesses to Null locations to be completed in 50% less time and consume 40% less energy than accesses to valid Data locations. An experimental NCL-based address lookup system is then designed that includes all of the developed NCL modules. Statistical delay models derived from circuit-level simulations of individual modules are used to emulate realistic circuit delay variability in the behavioural modules written in Verilog. Simulations of the assembled system demonstrate that unlike what was observed with the synchronous design, with NCL, the design that does not employ Bloom filters, but only the Null-storage column RAMs for prefix storage, exhibits the smallest area on the chip and also consumes the least energy per address lookup. It is concluded that to derive maximum benefit out of an asynchronous design approach; it is necessary to carefully select the architectural blocks that combine the peculiarities of the implemented algorithm with the capabilities of the NCL design methodology