Building an Evolvable Low-Cost HW/SW Educational Platform--Application to Virtual Instrumentation

This paper describes a hardware/software FPGA-based platform. Its goal is to provide a reusable low-cost system for teaching system-level design, with an emphasis on design reuse as an effective mean to cope with an ever growing design complexity. An open source strategy promotes cross-university collaboration by relying on previously developed software. The first implementation examples target the area of Reconfigurable Virtual Instrumentation (RVI), which in turn provides a low-cost solution for teaching electronic instrumentation

High Performance 128-Channel Acquisition System for Electrophysiological Signals

The increased popularity of investigations and exploits in the fields of neurological rehabilitation, human emotion recognition, and other relevant brain-computer interfaces demand the need for flexible electrophysiology data acquisition systems. Such systems often require to be multi-modal and multi-channel capable of acquiring and processing several different types of physiological signals simultaneously in realtime. Developments of modular and scalable electrophysiological data acquisition systems for experimental research enhance understanding and progress in the field. To contribute to such an endeavor, we present an open-source hardware project called High-Channel Count Electrophysiology or HiCCE, targeting to produce an easily-adaptable, cost-effective, and affordable electrophysiological acquisition system as an alternative solution for mostly available commercial tools and the current state of the art in the field. In this paper, we describe the design and validation of the entire chain of the HiCCE-128 electrophysiological data acquisition system. The system comprises of 128 independent channels capable of acquiring signal at 31.25 kHz, with 16 effective bits per channel with a measured noise level of about 3 μV. The reliability and feasibility of the implemented system have been confirmed through a series of tests and real-world applications. The modular design methodology based on the FPGA Mezzanine Card (FMC) standard allows the connection of the HiCCE-128 board to programmable system-on-chip carrier devices through the high-speed FMC link. The implemented architecture enables end users to add various high-response electrophysiological signal processing techniques in the field programmable gate arrays (FPGA) part of the system on chip (SoC) device on each channel in parallel according to application specification