Multilevel multistate hybrid voltage regulator

In this work, a new set of voltage regulators as well as some controlling methods and schemes are proposed. While normal switched capacitor voltage regulators are easy integrable, they are suffering from charge sharing losses as well as fast degradation of efficiency when deviating from target operation point. On the other hand, conventional buck converters use bulky magnetic components that introduce challenges to integrate them on chip. The new set of voltage regulators covers the gap between inductor-based and capacitor-based voltage regulators by taking the advantages of both of them while avoiding or minimizing their disadvantages. The voltage regulator device consists of a switched capacitor circuit that is periodically switching its output between different voltage levels followed by a low pass filter to give a regulated output voltage. The voltage regulator is capable of converting an input voltage to a wide range of output voltage with a high efficiency that is roughly constant over the whole operation range. By switching between adjacent voltage levels, the voltage drop on the inductor is limited allowing for the use of smaller inductor sizes while maintaining the same performance. The general concept of the proposed voltage regulator as well as some operating conditions and techniques are explained. A phase interleaving technique to operate the multilevel multistate voltage regulator has been proposed. In this technique, the phases of two or more voltage levels are interleaved which enhances the effective switching frequency of the charge transferring components. This results in a further boost in the proposed regulator\u27s performance. A 4-level 4-state hybrid voltage regulator has been introduced as an application on the proposed concepts and techniques. It shows better performance compared to both integrated inductor-based and capacitor-based voltage regulators. The results prove that the proposed set of voltage regulators offers a potential move towards easing the integration of voltage regulators on chip with a performance that approaches that of off-chip voltage regulators

Body-bias-driven design strategy for area and performance efficient CMOS circuits

Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum speed specifications and costs additional power due to area over-dimensioning during synthesis. We present a new design synthesis strategy for digital CMOS circuits that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. An in-depth analysis of the body-bias-driven design theory is provided. It is complemented by an algorithm that enables fast reconstruction of the area-clock period tradeoff curve of the design. We validated these new concepts through industrial processor designs in 90-nm low-power CMOS. For standard- $V_{rm th}$ implementations, we observed performance-per-area improvements up to 40%, area and leakage reductions up to 30%, and dynamic power savings of up to 10% without performance penalties as a benefit from our proposed body-bias-driven design strategy. The benefits are larger for high-$V_{rm th}$ implementations. In this case, we observed performance-per-area improvements up to 90%, area and leakage reductions up to 40%, and dynamic power savings of up to 25% without performance penalties

Body-bias-driven design strategy for area and performance efficient CMOS circuits

Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum speed specifications and costs additional power due to area over-dimensioning during synthesis. We present a new design synthesis strategy for digital CMOS circuits that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. An in-depth analysis of the body-bias-driven design theory is provided. It is complemented by an algorithm that enables fast reconstruction of the area-clock period tradeoff curve of the design. We validated these new concepts through industrial processor designs in 90-nm low-power CMOS. For standard- $V_{rm th}$ implementations, we observed performance-per-area improvements up to 40%, area and leakage reductions up to 30%, and dynamic power savings of up to 10% without performance penalties as a benefit from our proposed body-bias-driven design strategy. The benefits are larger for high-$V_{rm th}$ implementations. In this case, we observed performance-per-area improvements up to 90%, area and leakage reductions up to 40%, and dynamic power savings of up to 25% without performance penalties

Tuning resistive switching in complex oxide memristors

The continuous demand of lightweight portable, cheap and low-power devices has pushed the electronic industry to the limits of the current technology. Flash memory technology which represents the mainstream non-volatile memories has experienced an impressive development over the last decade. This led their fabrication down to a 16 nm node and implementation of high-density 3D memory architectures. Due to the scaling limit of Flash technology, the need of new memories that combine the characteristics of a Flash but overcome the scaling limits is increasing. In this surge, oxide-based resistive memories – also called memristors – have emerged as a new family of storage-class memory. The extremely simple physical structure fast response, low cost and power consumption render resistive memories as a valid alternative of the Flash technology and an optimal choice for the next generation memory technology. The nanoscale resistive memories have demonstrated a variety of memory characteristics which depends on the electrochemical properties of the oxide system and several physical parameters including device structure and electrical biasing conditions. This indicates a complex nature of the underlying microscopic switching mechanisms which require a thorough understanding in order to fully benefit from the virtue of this technology. The work presented in this Doctoral Dissertation focuses on the realization and fine tuning the memory characteristics of SrTiO3 based resistive switching memories. A novel synthesis route is adopted to realize highly complementary metal oxide semiconductor (CMOS) compatible nanoscale memristive devices and engineer the composition of the functional SrTiO3 perovskite oxide. By following the novel synthesis approach, SrTiO3 memristive devices with different stoichiometry such as different concentration of oxygen vacancies, metallic dopant species and physical structures are fabricated to achieve multifunctional characteristics of these devices. Rigorous electrical and material characterizations are carried out to analyze the resistive switching performance and understand the underlying microscopic mechanisms. Stable multi-state resistive switching is demonstrated in donor (Nb) doped oxygen-deficient amorphous SrTiO3 (Nb:a-STOx) memories. The dynamics of multi-state switching behavior and the effect of Nb-doping on tuning the resistive switching are investigated by utilizing a combination of interfacial compositional evaluation and activation energy measurements. Furthermore, multiple switching behaviors in a single acceptor (Cr) doped amorphous SrTiO3 (Cr:a-STOx) memory cell are demonstrated. A physical model is also suggested to explain the novel switching characteristics of these versatile memristive devices. A highly transparent and multifunctional SrTiO3 based memory system is fabricated which offers a reliable data storage and photosensitive platform for further transparent electronics. Also a unique photoluminescence mapping is presented as an identification technique for localized conduction mechanism in oxide resistive memories. Finally, SrTiO3 resistive memories are engineered to mimic biological synapses. A hybrid CMOS-memristor approached is presented to demonstrate first implementation of higher order time and rate dependent synaptic learning rules. Furthermore, these artificial synapses are tuned for energy-efficient performance to highlight their potential for the future neuromorphic networks