4,427 research outputs found
High throughput spatial convolution filters on FPGAs
Digital signal processing (DSP) on field- programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks can offer more efficient mapping of DSP computations, they are primarily designed for 1-D filter structures. We present a study on spatial convolutional filter implementations on FPGAs, optimizing around the structure of the DSP blocks to offer high throughput while maintaining the coefficient flexibility that other published architectures usually sacrifice. We show that it is possible to implement large filters for large 4K resolution image frames at frame rates of 30â60 FPS, while maintaining functional flexibility
On the Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpression Elimination Methods
No abstract availabl
To Develop and Implement Low Power, High Speed VLSI for Processing Signals using Multirate Techniques
Multirate technique is necessary for systems with different input and output sampling rates. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems [4]. This Paper presents Multirate modules used for filtering to provide signal processing in wireless communication system. Many architecture developed for the design of low complexity, bit parallel Multiple Constant Multiplications operation which dominates the complexity of DSP systems. However, major drawbacks of present approaches are either too costly or not efficient enough. On the other hand, MCM and digit-serial adder offer alternative low complexity designs, since digit-serial architecture occupy less area and are independent of the data word length [1][10]. Multiple Constant Multiplications is efficient way to reduce the number of addition and subtraction in polyphase filter implementation. This Multirate design methodology is systematic and applicable to many problems. In this paper, attention has given to the MCM & digit serial architecture with shifting and adding techniques that offers alternative low complexity in operations. This paper also focused on Multirate Signal Processing Modules using Voltage and Technology scaling. Reduction of power consumption is important for VLSI system and also it becomes one of the most critical design parameter. Transistorized Multirate module which has full custom design with different circuit topology and optimization level simulated on cadence platform. Multirate modules are used AMI 0.6 um, TSMC 0.35 um, and TSMC 0.25 um technologies for different voltage scaling. The presented methodology provides a systematic way to derive circuit technique for high speed operation at a low supply voltage. Multirate polyphase interpolator and decimator are also designed and optimized at architectural level in order to analyze the terms power consumption, area and speed.
DOI: 10.17762/ijritcc2321-8169.150314
Online self-repair of FIR filters
Chip-level failure detection has been a target of research for some time, but today's very deep-submicron technology is forcing such research to move beyond detection. Repair, especially self-repair, has become very important for containing the susceptibility of today's chips. This article introduces a self-repair-solution for the digital FIR filter, one of the key blocks used in DSPs
NIKEL: Electronics and data acquisition for kilopixels kinetic inductance camera
A prototype of digital frequency multiplexing electronics allowing the real
time monitoring of microwave kinetic inductance detector (MKIDs) arrays for
mm-wave astronomy has been developed. Thanks to the frequency multiplexing, it
can monitor simultaneously 400 pixels over a 500 MHz bandwidth and requires
only two coaxial cables for instrumenting such a large array. The chosen
solution and the performances achieved are presented in this paper.Comment: 21 pages, 14 figure
Optimal design of linear phase FIR digital filters with very flat passbands and equiripple stopbands
A new technique is presented for the design of digital FIR filters, with a prescribed degree of flatness in the passband, and a prescribed (equiripple) attenuation in the stopband. The design is based entirely on an appropriate use of the well-known Reméz-exchange algorithm for the design of weighted Chebyshev FIR filters. The extreme versatility of this algorithm is combined with certain "maximally flat" FIR filter building blocks, in order to generate a wide family of filters. The design technique directly leads to structures that have low passband sensitivity properties
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