Design of a Hybrid Modular Switch

Network Function Virtualization (NFV) shed new light for the design, deployment, and management of cloud networks. Many network functions such as firewalls, load balancers, and intrusion detection systems can be virtualized by servers. However, network operators often have to sacrifice programmability in order to achieve high throughput, especially at networks' edge where complex network functions are required. Here, we design, implement, and evaluate Hybrid Modular Switch (HyMoS). The hybrid hardware/software switch is designed to meet requirements for modern-day NFV applications in providing high-throughput, with a high degree of programmability. HyMoS utilizes P4-compatible Network Interface Cards (NICs), PCI Express interface and CPU to act as line cards, switch fabric, and fabric controller respectively. In our implementation of HyMos, PCI Express interface is turned into a non-blocking switch fabric with a throughput of hundreds of Gigabits per second. Compared to existing NFV infrastructure, HyMoS offers modularity in hardware and software as well as a higher degree of programmability by supporting a superset of P4 language

Packet Transactions: High-level Programming for Line-Rate Switches

Many algorithms for congestion control, scheduling, network measurement, active queue management, security, and load balancing require custom processing of packets as they traverse the data plane of a network switch. To run at line rate, these data-plane algorithms must be in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chipsets. The key challenge is that these algorithms create and modify algorithmic state. The key idea to achieve line-rate programmability for stateful algorithms is the notion of a packet transaction : a sequential code block that is atomic and isolated from other such code blocks. We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient and natural way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated die-area overhead.Comment: 16 page

Performance Comparison of 112 Gb/s DMT, Nyquist PAM4 and Partial-Response PAM4 for Future 5G Ethernet-based Fronthaul Architecture

For a future 5G Ethernet-based fronthaul architecture, 100G trunk lines of a transmission distance up to 10 km over a standard single-mode fiber (SSMF) in combination with cheap gray optics to daisy chain cell site network interfaces are a promising cost- and power-efficient solution. For such a scenario, different intensity modulation and direct detect formats at a data rate of 112 Gb/s, namely Nyquist four-level pulse amplitude modulation (PAM4), discrete multitone transmission (DMT), and partial-response (PR) PAM4, are experimentally investigated, using a low-cost electroabsorption modulated laser, a 25G driver, and current state-of-the-art high-speed 84-GS/s CMOS digital-to-analog converter and analog-to-digital converter test chips. Each modulation format is optimized independently for the desired scenario, and their digital signal processing requirements are investigated. The performance of Nyquist PAM4 and PR PAM4 depends very much on the efficiency of pre- and postequalization. We show the necessity for at least 11 feedforward equalizer (FFE) taps for pre-emphasis and up to 41 FFE coefficients at the receiver side. In addition, PR PAM4 requires a maximum likelihood sequence estimation with four states to decode the signal back to a PAM4 signal. On the contrary, bit loading and power loading are crucial for DMT, and an FFT length of at least 512 is necessary. With optimized parameters, all modulation formats result in a very similar performances, demonstrating a transmission distance of up to 10 km over an SSMF with bit error rates below an FEC threshold of 4.4E-3, allowing error-free transmission

Coarse wavelength division multiplexer on silicon-on-insulator for 100 GbE

A four-channel cascaded MZl based de-multiplexer at O-band with coarse channel spacing of 20 nm and band flatness of 13 nm is demonstrated on silicon-on-insulator. The device shows a mean crosstalk and insertion loss below -16 dB and 2.5 dB

Key Signal Processing Technologies for High-speed Passive Optical Networks

With emerging technologies such as high-definition video, virtual reality, and cloud computing, bandwidth demand in the access networks is ever-increasing. Passive optical network (PON) has become a promising architecture thanks to its low cost and easy management. IEEE and ITU-T standard organizations have been standardizing the next-generation PON, targeting on increasing the single-channel capacity from 10 Gb/s to 25, 50, and 100 Gb/s as the solution to address the dramatic increase of bandwidth demand. However, since the access network is extremely cost-sensitive, many research problems imposed in the physical layer of PON need to be addressed in a cost-efficient way, which is the primary focus of this thesis. Utilizing the low-cost 10G optics to build up high-speed PON systems is a promising approach, where signal processing techniques are key of importance. Two categories of signal processing techniques have been extensively investigated, namely optical signal processing (OSP) and digital signal processing (DSP). Dispersion-supported equalization (DSE) as a novel OSP scheme is proposed to achieve bit-rate enhancement from 10 Gb/s to 25 Gb/s based on 10G class of optics. Thanks to the bandwidth improved by DSE, the non-return-zero on-off keying which is the simplest modulation format is able to be adopted in the PON system without complex modulation or DSP. Meanwhile, OSP is also proposed to work together with DSP enabling 50G PON while simplifying the DSP complexity. Using both DSE and simple feed-forward equalizer is able to support 50 Gb/s PAM-4 transmission with 10G optics. For C-band 50 Gb/s transmission, injection locking techniques as another OSP approach is proposed to compress the directly modulated laser chirp and increase system bandwidth in the optical domain where a doubled capacity from 25 Gb/s to 50 Gb/s over 20 km fiber can be built on top of 10G optics. For DSP, we investigated the advantages of neural network (NN) on the mitigation of the time-varying nonlinear semiconductor optical amplifier pattern effect. In order to reduce the expense caused by the high computation complexity of NN, a pre- equalizer is introduced at the central office that allows cost sharing for all connected access users. In order to push the PON system line rate to 100 Gb/s, a joint nonlinear Tomlinson- Harashima precoding-Volterra algorithm is proposed to compensate for both linear and nonlinear distortions where 100 Gb/s PAM-4 transmission over 20 km fiber with 15 GHz system bandwidth can be achieved